[PATCH]: 36cf6b0a2c target/xtensa: fix clang analyzer warning

[gerrit]

This is an automated email from Gerrit.

"Ian Thompson <ia...@cadence.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/7198

-- gerrit

commit 36cf6b0a2c47797aa59625eb91317c3ed36776f8
Author: Ian Thompson <ia...@cadence.com>
Date:   Thu Sep 15 16:24:33 2022 -0700

    target/xtensa: fix clang analyzer warning
    
    Reworked xtensa_queue_exec_ins_wide() logic to properly handle endian 
issues while executing arbitrary instructions.
    
    Signed-off-by: Ian Thompson <ia...@cadence.com>
    Change-Id: I5752dd254ce8b8822886ffc7edecaa242a93cce8

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index a6e50ccc71..2aec7afcaf 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -498,17 +498,20 @@ static void xtensa_queue_exec_ins(struct xtensa *xtensa, 
uint32_t ins)
 
 static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, 
uint8_t oplen)
 {
-       if ((oplen > 0) && (oplen <= 64)) {
-               uint32_t opsw[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };  /* 8 DIRx regs: 
max width 64B */
-               uint8_t oplenw = (oplen + 3) / 4;
-               if (xtensa->target->endianness == TARGET_BIG_ENDIAN)
-                       buf_bswap32((uint8_t *)opsw, ops, oplenw * 4);
-               else
-                       memcpy(opsw, ops, oplen);
+       const int max_oplen = 64;       /* 8 DIRx regs: max width 64B */
+       if ((oplen > 0) && (oplen <= max_oplen)) {
+               uint8_t ops_padded[max_oplen];
+               memcpy(ops_padded, ops, oplen);
+               memset(ops_padded + oplen, 0, max_oplen - oplen);
+               uint8_t oplenw = DIV_ROUND_UP(oplen, 4);
                for (int32_t i = oplenw - 1; i > 0; i--)
-                       xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0 + i, 
opsw[i]);
+                       xtensa_queue_dbg_reg_write(xtensa,
+                               XDMREG_DIR0 + i,
+                               target_buffer_get_u32(xtensa->target, 
&ops_padded[i]));
                /* Write DIR0EXEC last */
-               xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0EXEC, opsw[0]);
+               xtensa_queue_dbg_reg_write(xtensa,
+                       XDMREG_DIR0EXEC,
+                       target_buffer_get_u32(xtensa->target, &ops_padded[0]));
        }
 }
 

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