That seems reasonable, unless a core could somehow be specified, which
would mean adding a resume command at the processor level (arm, aarch64)
level. Probably not hard to do.
As for address, I don't see that it would ever make sense for all cores
to resume at the same address.
So if the resume address is specified in a multi-core configuration,
then either:
1) only that core should resume, or
2) all other cores also resume at their respective current addresses.
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On 3/28/23 13:38, Tommy Murphy wrote:
FWIW, my reading of the OpenOCD docs is that where SMP mode is enabled
then resume (and halt) take effect on all cores/threads in the SMP
group. That seems to be the case wherever the two are mentioned
together in the user documentation. Whether or not that is appropriate
in all cases, particularly all RISC-V cases, is not clear to me.
