This is an automated email from Gerrit.
"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/7574
-- gerrit
commit a0de90b6cfaeefd1b895f0d1780420ebc62fa960
Author: Tomas Vanek <van...@fbl.cz>
Date: Sun Apr 2 18:27:17 2023 +0200
target/arm_adi_v5: simplify TI BE 32 quirk workaround
Introduce ti_be_lane_xor for byte lane correction
and use common code for conversion.
Change-Id: I6a30672b908770323d30813a714e06ab8695fe26
Signed-off-by: Tomas Vanek <van...@fbl.cz>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index ee6fd206be..e6bf910f69 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -338,7 +338,6 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t
*buffer, uint32_t siz
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE :
CSW_ADDRINC_OFF;
uint32_t csw_size;
- target_addr_t addr_xor;
int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
@@ -354,15 +353,17 @@ static int mem_ap_write(struct adiv5_ap *ap, const
uint8_t *buffer, uint32_t siz
* setting the TAP, and we set the TAP after every transfer rather then
relying on
* address increment. */
+ target_addr_t ti_be_lane_xor = dap->ti_be_32_quirks ? 3 : 0;
+ target_addr_t ti_be_addr_xor;
if (size == 4) {
csw_size = CSW_32BIT;
- addr_xor = 0;
+ ti_be_addr_xor = 0;
} else if (size == 2) {
csw_size = CSW_16BIT;
- addr_xor = dap->ti_be_32_quirks ? 2 : 0;
+ ti_be_addr_xor = dap->ti_be_32_quirks ? 2 : 0;
} else if (size == 1) {
csw_size = CSW_8BIT;
- addr_xor = dap->ti_be_32_quirks ? 3 : 0;
+ ti_be_addr_xor = dap->ti_be_32_quirks ? 3 : 0;
} else {
return ERROR_TARGET_UNALIGNED_ACCESS;
}
@@ -385,7 +386,7 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t
*buffer, uint32_t siz
if (retval != ERROR_OK)
break;
- retval = mem_ap_setup_tar(ap, address ^ addr_xor);
+ retval = mem_ap_setup_tar(ap, address ^ ti_be_addr_xor);
if (retval != ERROR_OK)
return retval;
@@ -393,23 +394,7 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t
*buffer, uint32_t siz
* depends on the type of transfer and alignment. See ARM
document IHI0031C. */
uint32_t outvalue = 0;
uint32_t drw_byte_idx = address;
- if (dap->ti_be_32_quirks) {
- switch (this_size) {
- case 4:
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^
(drw_byte_idx++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^
(drw_byte_idx++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^
(drw_byte_idx++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^
(drw_byte_idx & 3) ^ addr_xor);
- break;
- case 2:
- outvalue |= (uint32_t)*buffer++ << 8 * (1 ^
(drw_byte_idx++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (1 ^
(drw_byte_idx & 3) ^ addr_xor);
- break;
- case 1:
- outvalue |= (uint32_t)*buffer++ << 8 * (0 ^
(drw_byte_idx & 3) ^ addr_xor);
- break;
- }
- } else if (dap->nu_npcx_quirks) {
+ if (dap->nu_npcx_quirks) {
switch (this_size) {
case 4:
outvalue |= (uint32_t)*buffer++ << 8 *
(drw_byte_idx++ & 3);
@@ -432,14 +417,14 @@ static int mem_ap_write(struct adiv5_ap *ap, const
uint8_t *buffer, uint32_t siz
} else {
switch (this_size) {
case 4:
- outvalue |= (uint32_t)*buffer++ << 8 *
(drw_byte_idx++ & 3);
- outvalue |= (uint32_t)*buffer++ << 8 *
(drw_byte_idx++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 *
((drw_byte_idx++ & 3) ^ ti_be_lane_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 *
((drw_byte_idx++ & 3) ^ ti_be_lane_xor);
/* fallthrough */
case 2:
- outvalue |= (uint32_t)*buffer++ << 8 *
(drw_byte_idx++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 *
((drw_byte_idx++ & 3) ^ ti_be_lane_xor);
/* fallthrough */
case 1:
- outvalue |= (uint32_t)*buffer++ << 8 *
(drw_byte_idx & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 *
((drw_byte_idx & 3) ^ ti_be_lane_xor);
}
}
--
