[PATCH]: 45fd3b1447 target/arm_adi_v5, cortex_m: error messages in case of unaligned access

[gerrit]

This is an automated email from Gerrit.

"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which 
you can find at https://review.openocd.org/c/openocd/+/7577

-- gerrit

commit 45fd3b14473d2cb26068576ad60e3144213ac71c
Author: Tomas Vanek <van...@fbl.cz>
Date:   Sun Apr 2 21:46:12 2023 +0200

    target/arm_adi_v5, cortex_m: error messages in case of unaligned access
    
    Memory read and write commands silently fail when
    ERROR_TARGET_UNALIGNED_ACCESS is returned:
    
     [rp2040.core0] Cortex-M0+ r0p1 processor detected
     ...
     > mdw 0x20000001
    
     > mww 0x20000001 0
    
    Add error messages to mem_ap_read/write() routines.
    
    Set debug_ap->unaligned_access_bad if detected ARMv6-M core
    instead of the duplicated Cortex-M specific alignment checking.
    
    Change-Id: I4f297e64250c0647be03b7a649f9d0d708a7ad71
    Signed-off-by: Tomas Vanek <van...@fbl.cz>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 34166770e8..efce9a6114 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -504,8 +504,10 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t 
*buffer, uint32_t siz
                }
        }
 
-       if (ap->unaligned_access_bad && (address % size != 0))
+       if (ap->unaligned_access_bad && (address % size != 0)) {
+               LOG_ERROR("Unaligned write at " TARGET_ADDR_FMT ", size %u", 
address, size);
                return ERROR_TARGET_UNALIGNED_ACCESS;
+       }
 
        /* Nuvoton NPCX quirks prevent packed writes */
        bool pack = !dap->nu_npcx_quirks;
@@ -615,8 +617,10 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t 
*buffer, uint32_t size, uint
                return ERROR_TARGET_SIZE_NOT_SUPPORTED;
        }
 
-       if (ap->unaligned_access_bad && (adr % size != 0))
+       if (ap->unaligned_access_bad && (adr % size != 0)) {
+               LOG_ERROR("Unaligned read at " TARGET_ADDR_FMT ", size %u", 
adr, size);
                return ERROR_TARGET_UNALIGNED_ACCESS;
+       }
 
        /* Allocate buffer to hold the sequence of DRW reads that will be made. 
This is a significant
         * over-allocation if packed transfers are going to be used, but 
determining the real need at
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 88e9bb299f..1c78311fcf 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2153,12 +2153,6 @@ static int cortex_m_read_memory(struct target *target, 
target_addr_t address,
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
 
-       if (armv7m->arm.arch == ARM_ARCH_V6M) {
-               /* armv6m does not handle unaligned memory access */
-               if (((size == 4) && (address & 0x3u)) || ((size == 2) && 
(address & 0x1u)))
-                       return ERROR_TARGET_UNALIGNED_ACCESS;
-       }
-
        return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
 }
 
@@ -2167,12 +2161,6 @@ static int cortex_m_write_memory(struct target *target, 
target_addr_t address,
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
 
-       if (armv7m->arm.arch == ARM_ARCH_V6M) {
-               /* armv6m does not handle unaligned memory access */
-               if (((size == 4) && (address & 0x3u)) || ((size == 2) && 
(address & 0x1u)))
-                       return ERROR_TARGET_UNALIGNED_ACCESS;
-       }
-
        return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
 }
 
@@ -2551,6 +2539,10 @@ int cortex_m_examine(struct target *target)
 
                armv7m->arm.arch = cortex_m->core_info->arch;
 
+               /* ARMv6-M  does not handle unaligned memory access */
+               if (armv7m->arm.arch == ARM_ARCH_V6M)
+                       armv7m->debug_ap->unaligned_access_bad = true;
+
                LOG_TARGET_INFO(target, "%s r%" PRId8 "p%" PRId8 " processor 
detected",
                                cortex_m->core_info->name,
                                (uint8_t)((cpuid >> 20) & 0xf),

--