This is an automated email from Gerrit.
"Walter J. <walter...@oss.cipunited.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7912
-- gerrit
commit 8c3e48ecce9378bd0e68e3a217bf3d638b06a96b
Author: Walter Ji <walter...@oss.cipunited.com>
Date: Tue Sep 26 17:21:42 2023 +0800
target/mips32: add cpu info detection
Add detection for mips cpu types by using prid.
Change-Id: I28573b7c51783628db986bad0e226dcc399b4fa6
Signed-off-by: Walter Ji <walter...@oss.cipunited.com>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 573ad87c13..8746dd8f5c 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -306,7 +306,9 @@ int mips32_save_context(struct target *target)
struct mips32_common *mips32 = target_to_mips32(target);
/* read core registers */
- mips32_pracc_read_regs(mips32);
+ int retval = mips32_pracc_read_regs(mips32);
+ if (retval != ERROR_OK)
+ return retval;
for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (!mips32->core_cache->reg_list[i].valid)
@@ -329,9 +331,9 @@ int mips32_restore_context(struct target *target)
}
/* write core regs */
- mips32_pracc_write_regs(mips32);
+ int retval = mips32_pracc_write_regs(mips32);
- return ERROR_OK;
+ return retval;
}
int mips32_arch_state(struct target *target)
@@ -760,6 +762,196 @@ static int mips32_read_c0_prid(struct target *target)
return retval;
}
+static uint32_t mips32_determine_amd_cpu(uint32_t prid, const char **cpu_name)
+{
+ uint32_t cpu_type = MIPS32_CPU_UNKNOWN;
+
+ switch ((prid >> 24) & 0xff) {
+ case 0x00:
+ *cpu_name = "AMD Alchemy AU1000";
+ cpu_type = MIPS32_CPU_AU1000;
+ break;
+
+ case 0x01:
+ *cpu_name = "AMD Alchemy AU1500";
+ cpu_type = MIPS32_CPU_AU1500;
+ break;
+
+ case 0x02:
+ *cpu_name = "AMD Alchemy AU1100";
+ cpu_type = MIPS32_CPU_AU1100;
+ break;
+
+ case 0x03:
+ *cpu_name = "AMD Alchemy AU1550";
+ cpu_type = MIPS32_CPU_AU1550;
+ break;
+
+ case 0x04:
+ *cpu_name = "AMD Alchemy AU1200";
+ cpu_type = MIPS32_CPU_AU1200;
+ break;
+ }
+
+ return cpu_type;
+}
+
+static uint32_t mips32_determine_mti_cpu(uint32_t prid, const char **cpu_name)
+{
+ uint32_t cpu_type = MIPS32_CPU_UNKNOWN;
+
+ switch ((prid >> 8) & 0xff) { /* MIPS Technologies cores */
+ case 0x80:
+ *cpu_name = "MIPS 4Kc";
+ cpu_type = MIPS32_CPU_4KC;
+ break;
+
+ case 0x81:
+ *cpu_name = "MIPS 5Kc";
+ cpu_type = MIPS32_CPU_5KC;
+ break;
+
+ case 0x82:
+ *cpu_name = "MIPS 20Kc";
+ cpu_type = MIPS32_CPU_20KC;
+ break;
+
+ case 0x83:
+ *cpu_name = "MIPS 4KM";
+ cpu_type = MIPS32_CPU_4KM;
+ break;
+
+ case 0x84:
+ case 0x90:
+ *cpu_name = "MIPS 4KEc";
+ cpu_type = MIPS32_CPU_4KEC;
+ break;
+
+ case 0x85:
+ case 0x91:
+ *cpu_name = "MIPS 4KEm";
+ cpu_type = MIPS32_CPU_4KEM;
+ break;
+
+ case 0x86:
+ *cpu_name = "MIPS 4KSc";
+ cpu_type = MIPS32_CPU_4KSC;
+ break;
+
+ case 0x87:
+ *cpu_name = "MIPS M4k";
+ cpu_type = MIPS32_CPU_M4K;
+ break;
+
+ case 0x88:
+ *cpu_name = "MIPS 25Kf";
+ cpu_type = MIPS32_CPU_25KF;
+ break;
+
+ case 0x89:
+ *cpu_name = "MIPS 5KEc";
+ cpu_type = MIPS32_CPU_5KEC;
+ break;
+
+ case 0x92:
+ *cpu_name = "MIPS 4KSD";
+ cpu_type = MIPS32_CPU_4KSD;
+ break;
+
+ case 0x93:
+ *cpu_name = "MIPS 24Kc";
+ cpu_type = MIPS32_CPU_24KC;
+ break;
+
+ case 0x95:
+ *cpu_name = "MIPS 34Kc";
+ cpu_type = MIPS32_CPU_34KC;
+ break;
+
+ case 0x96:
+ *cpu_name = "MIPS 24KEc";
+ cpu_type = MIPS32_CPU_24KEC;
+ break;
+
+ case 0x97:
+ *cpu_name = "MIPS 74Kc";
+ cpu_type = MIPS32_CPU_74KC;
+ break;
+
+ case 0x99:
+ *cpu_name = "MIPS 1004Kc";
+ cpu_type = MIPS32_CPU_1004KC;
+ break;
+
+ case 0x9A:
+ *cpu_name = "MIPS 1074Kc";
+ cpu_type = MIPS32_CPU_1074KC;
+ break;
+
+ case 0x9B:
+ *cpu_name = "MIPS M14k";
+ cpu_type = MIPS32_CPU_M14K;
+ break;
+
+ case 0x9C:
+ *cpu_name = "MIPS M14Kc";
+ cpu_type = MIPS32_CPU_M14KC;
+ break;
+
+ case 0x9D:
+ *cpu_name = "MIPS M14KE";
+ cpu_type = MIPS32_CPU_M14KE;
+ break;
+
+ case 0x9E:
+ *cpu_name = "MIPS M14KEc";
+ cpu_type = MIPS32_CPU_M14KEC;
+ break;
+
+ case 0xA0:
+ *cpu_name = "MIPS interAptiv";
+ cpu_type = MIPS32_CPU_INTERAPTIV;
+ break;
+
+ case 0xA1:
+ *cpu_name = "MIPS interAptiv_CM";
+ cpu_type = MIPS32_CPU_INTERAPTIV_CM;
+ break;
+
+ case 0xA2:
+ *cpu_name = "MIPS proAptiv";
+ cpu_type = MIPS32_CPU_PROAPTIV;
+ break;
+
+ case 0xA3:
+ *cpu_name = "MIPS proAptiv_CM";
+ cpu_type = MIPS32_CPU_PROAPTIV_CM;
+ break;
+
+ case 0xA6:
+ *cpu_name = "MIPS M5100";
+ cpu_type = MIPS32_CPU_M5100;
+ break;
+
+ case 0xA7:
+ *cpu_name = "MIPS M5150";
+ cpu_type = MIPS32_CPU_M5150;
+ break;
+
+ case 0xA8:
+ *cpu_name = "MIPS P5600";
+ cpu_type = MIPS32_CPU_P5600;
+ break;
+
+ case 0xA9:
+ *cpu_name = "MIPS I5500";
+ cpu_type = MIPS32_CPU_I5500;
+ break;
+ }
+
+ return (cpu_type);
+}
+
/*
* Detect processor type and apply required quirks.
*
@@ -772,6 +964,7 @@ int mips32_cpu_probe(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
const char *cpu_name = "unknown";
+ uint32_t cpu_type = MIPS32_CPU_UNKNOWN;
int retval;
if (mips32->prid)
@@ -792,12 +985,54 @@ int mips32_cpu_probe(struct target *target)
break;
}
break;
+
+ case PRID_COMP_ALTERA:
+ cpu_name = "Altera";
+ cpu_type = MIPS32_CPU_MP32;
+ break;
+
+ case PRID_COMP_BROADCOM:
+ cpu_name = "Broadcom";
+ cpu_type = MIPS32_CPU_BCM;
+ break;
+
+ case PRID_COMP_LEXRA:
+ cpu_name = "Lexra";
+ cpu_type = MIPS32_CPU_LEXRA;
+ break;
+
+ case PRID_COMP_ALCHEMY:
+ cpu_type = mips32_determine_amd_cpu(mips32->prid, &cpu_name);
+ break;
+
default:
+ // None of the special cases? Then it should be generic MIPS
Tech(MTI) cpu.
+ cpu_type = mips32_determine_mti_cpu(mips32->prid, &cpu_name);
break;
}
LOG_DEBUG("CPU: %s (PRId %08x)", cpu_name, mips32->prid);
+ /* Determine which CP0 registers are available in the current processor
core */
+ switch (cpu_type) {
+ case MIPS32_CPU_M14KE:
+ mips32->cp0_mask = MIPS_CP0_MAPTIV_UC;
+ break;
+ case MIPS32_CPU_M14KEC:
+ case MIPS32_CPU_M5150:
+ mips32->cp0_mask = MIPS_CP0_MAPTIV_UP;
+ break;
+ case MIPS32_CPU_INTERAPTIV:
+ case MIPS32_CPU_INTERAPTIV_CM:
+ mips32->cp0_mask = MIPS_CP0_IAPTIV;
+ break;
+ default:
+ mips32->cp0_mask = MIPS_CP0_MK4;
+ break;
+ }
+
+ LOG_USER("CPU type: 0x%08x, CP0 mask: 0x%08x", cpu_type,
mips32->cp0_mask);
+
return ERROR_OK;
}
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 2eb775be5e..c5a053b8dd 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -265,6 +265,93 @@ enum mips32_isa_rel {
MIPS32_RELEASE_UNKNOWN,
};
+#define MIPS32_CORE_4K 0x0000
+#define MIPS32_CORE_4KE 0x0100
+#define MIPS32_CORE_4KS 0x0200
+#define MIPS32_CORE_5K 0x0400
+#define MIPS32_CORE_20K 0x0800
+#define MIPS32_CORE_M4K 0x1000
+#define MIPS32_CORE_24K 0x2000
+#define MIPS32_CORE_34K 0x4000
+#define MIPS32_CORE_AU1 0x8000
+#define MIPS32_CORE_24KE 0x10000
+#define MIPS32_CORE_74K 0x20000
+#define MIPS32_CORE_84K 0x40000
+#define MIPS32_CORE_BCM 0x80000
+#define MIPS32_CORE_1004K 0x100000
+#define MIPS32_CORE_1074K 0x200000
+#define MIPS32_CORE_M14K 0x400000
+#define MIPS32_CORE_ALTERA 0x800000
+#define MIPS32_CORE_PROAPTIV 0x1000000
+#define MIPS32_CORE_INTERAPTIV 0x2000000
+#define MIPS32_CORE_5KE 0x4000000
+#define MIPS32_CORE_P5600 0x8000000
+#define MIPS32_CORE_I5500 0x10000000
+#define MIPS32_CORE_LEXRA 0x20000000
+
+#define MIPS32_CORE_MASK 0xFFFFFF00
+#define MIPS32_VARIANT_MASK 0x00FF
+
+enum mips32_cpu_type {
+ MIPS32_CPU_UNKNOWN = 0,
+ MIPS32_CPU_4KC = 0x0001 | MIPS32_CORE_4K,
+ MIPS32_CPU_4KM = 0x0002 | MIPS32_CORE_4K,
+ MIPS32_CPU_4KP = 0x0004 | MIPS32_CORE_4K,
+ MIPS32_CPU_4KEC = 0x0001 | MIPS32_CORE_4KE,
+ MIPS32_CPU_4KEM = 0x0002 | MIPS32_CORE_4KE,
+ MIPS32_CPU_4KEP = 0x0004 | MIPS32_CORE_4KE,
+ MIPS32_CPU_4KSC = 0x0001 | MIPS32_CORE_4KS,
+ MIPS32_CPU_4KSD = 0x0002 | MIPS32_CORE_4KS,
+ MIPS32_CPU_M4K = 0x0008 | MIPS32_CORE_M4K,
+ MIPS32_CPU_24KC = 0x0001 | MIPS32_CORE_24K,
+ MIPS32_CPU_24KF = 0x0010 | MIPS32_CORE_24K,
+ MIPS32_CPU_24KEC = 0x0001 | MIPS32_CORE_24KE,
+ MIPS32_CPU_24KEF = 0x0010 | MIPS32_CORE_24KE,
+ MIPS32_CPU_34KC = 0x0001 | MIPS32_CORE_34K,
+ MIPS32_CPU_34KF = 0x0010 | MIPS32_CORE_34K,
+ MIPS32_CPU_5KC = 0x0001 | MIPS32_CORE_5K,
+ MIPS32_CPU_5KF = 0x0010 | MIPS32_CORE_5K,
+ MIPS32_CPU_5KEC = 0x0001 | MIPS32_CORE_5KE,
+ MIPS32_CPU_5KEF = 0x0010 | MIPS32_CORE_5KE,
+ MIPS32_CPU_20KC = 0x0001 | MIPS32_CORE_20K,
+ MIPS32_CPU_25KF = 0x0010 | MIPS32_CORE_20K,
+ MIPS32_CPU_AU1000 = 0x0001 | MIPS32_CORE_AU1,
+ MIPS32_CPU_AU1100 = 0x0002 | MIPS32_CORE_AU1,
+ MIPS32_CPU_AU1200 = 0x0003 | MIPS32_CORE_AU1,
+ MIPS32_CPU_AU1500 = 0x0004 | MIPS32_CORE_AU1,
+ MIPS32_CPU_AU1550 = 0x0005 | MIPS32_CORE_AU1,
+ MIPS32_CPU_74KC = 0x0001 | MIPS32_CORE_74K,
+ MIPS32_CPU_74KF = 0x0010 | MIPS32_CORE_74K,
+ MIPS32_CPU_84KC = 0x0001 | MIPS32_CORE_84K,
+ MIPS32_CPU_84KF = 0x0010 | MIPS32_CORE_84K,
+ MIPS32_CPU_BCM = 0x0000 | MIPS32_CORE_BCM,
+ MIPS32_CPU_MP32 = 0x0000 | MIPS32_CORE_ALTERA,
+ MIPS32_CPU_1004KC = 0x0001 | MIPS32_CORE_1004K,
+ MIPS32_CPU_1004KF = 0x0010 | MIPS32_CORE_1004K,
+ MIPS32_CPU_1074KC = 0x0001 | MIPS32_CORE_1074K,
+ MIPS32_CPU_1074KF = 0x0010 | MIPS32_CORE_1074K,
+ MIPS32_CPU_M14KC = 0x0001 | MIPS32_CORE_M14K,
+ MIPS32_CPU_M14K = 0x0002 | MIPS32_CORE_M14K,
+ MIPS32_CPU_M14KF = 0x0010 | MIPS32_CORE_M14K,
+ /* now called microAptiv UC */
+ MIPS32_CPU_M14KE = 0x0020 | MIPS32_CORE_M14K,
+ /* now called microAptiv UCF */
+ MIPS32_CPU_M14KEF = 0x0030 | MIPS32_CORE_M14K,
+ /* now called microAptiv UP */
+ MIPS32_CPU_M14KEC = 0x0040 | MIPS32_CORE_M14K,
+ /* now called microAptiv UPF */
+ MIPS32_CPU_M14KECF = 0x0050 | MIPS32_CORE_M14K,
+ MIPS32_CPU_M5100 = 0x0090 | MIPS32_CORE_M14K,
+ MIPS32_CPU_M5150 = 0x00B0 | MIPS32_CORE_M14K,
+ MIPS32_CPU_PROAPTIV = 0x0001 | MIPS32_CORE_PROAPTIV,
+ MIPS32_CPU_PROAPTIV_CM = 0x0002 | MIPS32_CORE_PROAPTIV,
+ MIPS32_CPU_INTERAPTIV = 0x0001 | MIPS32_CORE_INTERAPTIV,
+ MIPS32_CPU_INTERAPTIV_CM = 0x0002 | MIPS32_CORE_INTERAPTIV,
+ MIPS32_CPU_P5600 = MIPS32_CORE_P5600,
+ MIPS32_CPU_I5500 = MIPS32_CORE_I5500,
+ MIPS32_CPU_LEXRA = 0x0000 | MIPS32_CORE_LEXRA,
+};
+
enum mips32_fp_imp {
MIPS32_FP_IMP_NONE = 0,
MIPS32_FP_IMP_32 = 1,
diff --git a/src/target/mips_cpu.h b/src/target/mips_cpu.h
index 8190b32e43..dd6389adde 100644
--- a/src/target/mips_cpu.h
+++ b/src/target/mips_cpu.h
@@ -12,7 +12,12 @@
/* Assigned Company values for bits 23:16 of the PRId register. */
#define PRID_COMP_MASK 0xff0000
-#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_MTI 0x010000
+#define PRID_COMP_BROADCOM 0x020000
+#define PRID_COMP_ALCHEMY 0x030000
+#define PRID_COMP_LEXRA 0x0b0000
+#define PRID_COMP_ALTERA 0x100000
#define PRID_COMP_INGENIC_E1 0xe10000
/*
--
