This is an automated email from Gerrit.
"Erhan Kurubas <erhan.kuru...@espressif.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8027
-- gerrit
commit 5133b24fb1e4b563a6ac1ce5126eb6a9b43934cd
Author: Erhan Kurubas <erhan.kuru...@espressif.com>
Date: Thu Nov 30 11:58:40 2023 +0100
loaders/espressif: add esp32s2 stub flasher application code
Special binary program running on the target (ESP32-S2) to perform
flash operations and communicate to the OpenOCD host.
Camelcase symbols comes from esp-idf
Checkpatch-ignore: CAMELCASE
Signed-off-by: Erhan Kurubas <erhan.kuru...@espressif.com>
Change-Id: I7c066eb36d4d2a925e35a66af5dfbe001216125f
diff --git a/contrib/loaders/flash/espressif/esp32s2/Makefile
b/contrib/loaders/flash/espressif/esp32s2/Makefile
new file mode 100644
index 0000000000..152dbde2c5
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/Makefile
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Makefile to compile flasher stub program
+# Copyright (C) 2021 Espressif Systems Ltd.
+
+# Prefix for ESP32-S2 cross compilers (can include a directory path)
+CROSS ?= xtensa-esp32s2-elf-
+
+# Path to the esp-idf root dir
+IDF_PATH ?= ../..
+
+STUB_ARCH := xtensa
+STUB_CHIP_PATH := $(shell pwd)
+STUB_COMMON_PATH := $(STUB_CHIP_PATH)/..
+STUB_CHIP_ARCH_PATH := $(STUB_COMMON_PATH)/$(STUB_ARCH)
+STUB_OBJ_DEPS := sdkconfig.h
+STUB_LD_SCRIPT := stub.ld
+STUB_CHIP := ESP32S2
+
+SRCS := $(IDF_PATH)/components/app_trace/port/$(STUB_ARCH)/port.c \
+ $(IDF_PATH)/components/xtensa/eri.c \
+ $(IDF_PATH)/components/esp_hw_support/port/esp32s2/rtc_clk.c \
+ $(IDF_PATH)/components/esp_hw_support/port/esp32s2/rtc_clk_init.c \
+ $(IDF_PATH)/components/esp_hw_support/port/esp32s2/rtc_time.c \
+ $(IDF_PATH)/components/esp_rom/patches/esp_rom_regi2c.c
+
+CFLAGS := -std=gnu99 -mlongcalls -mtext-section-literals
+
+INCLUDES := -I$(IDF_PATH)/components/esp32s2/include
-I$(IDF_PATH)/components/soc/esp32s2/include \
+ -I$(IDF_PATH)/components/esp_rom/include/esp32s2
-I$(IDF_PATH)/components/xtensa/esp32s2/include \
+ -I$(IDF_PATH)/components/hal/esp32s2/include
-I$(IDF_PATH)/components/esp_rom/esp32s2 \
+ -I$(IDF_PATH)/components/esp_hw_support/port/esp32s2/private_include \
+ -I$(IDF_PATH)/components/esp_hw_support/port/esp32s2 \
+
+DEFINES :=
+
+LDFLAGS := -L$(IDF_PATH)/components/esp32s2/ld
-T$(IDF_PATH)/components/esp_rom/esp32s2/ld/esp32s2.rom.ld \
+ -T$(IDF_PATH)/components/esp_rom/esp32s2/ld/esp32s2.rom.newlib-funcs.ld
\
+ -T$(IDF_PATH)/components/esp_rom/esp32s2/ld/esp32s2.rom.spiflash.ld
-T$(IDF_PATH)/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld \
+ -T$(IDF_PATH)/components/esp_rom/esp32s2/ld/esp32s2.rom.libgcc.ld
+
+include ../stub_common.mk
\ No newline at end of file
diff --git a/contrib/loaders/flash/espressif/esp32s2/sdkconfig.h
b/contrib/loaders/flash/espressif/esp32s2/sdkconfig.h
new file mode 100644
index 0000000000..fccaba9aa1
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/sdkconfig.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _STUB_SDKCONFIG_H_
+#define _STUB_SDKCONFIG_H_
+
+#define CONFIG_IDF_TARGET_ARCH_XTENSA 1
+#define CONFIG_IDF_TARGET_ESP32S2 1
+#define CONFIG_FREERTOS_UNICORE 1
+/* Use ROM flash driver patch
+ * #define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
+ * Disable application module multi-threading lock */
+#define CONFIG_APPTRACE_LOCK_ENABLE 0
+/* Enable apptarce module for flash data transfers */
+#define CONFIG_APPTRACE_DEST_JTAG 1
+#define CONFIG_APPTRACE_MEMBUFS_APPTRACE_PROTO_ENABLE 1
+#define CONFIG_APPTRACE_ENABLE 1
+#define CONFIG_APPTRACE_BUF_SIZE 0
+#define CONFIG_APPTRACE_PENDING_DATA_SIZE_MAX 0
+/* Debug UART number */
+#define CONFIG_CONSOLE_UART_NUM 0
+/* Debug UART baudrate */
+#define CONFIG_CONSOLE_UART_BAUDRATE 115200
+/* alloc apptrace data buffers on stack */
+#define CONFIG_STUB_STACK_DATA_POOL_SIZE (2 * CONFIG_APPTRACE_BUF_SIZE)
+
+/* needed due to apptrace sources usage */
+#define CONFIG_LOG_MAXIMUM_LEVEL 0
+/* needed due to various checks in IDF headers */
+#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
+/* TODO: use current clk, get it from PLL settings */
+#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 240
+/* Unused by stub, just for compilation of IDF */
+#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
+
+#endif /*_STUB_SDKCONFIG_H_ */
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub.ld
b/contrib/loaders/flash/espressif/esp32s2/stub.ld
new file mode 100644
index 0000000000..a4370a343a
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub.ld
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * LD script for ESP32-S2 flassher stub *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <ale...@espressif.com> *
+ ***************************************************************************/
+
+MEMORY {
+ /* Place sections by starting from the Internal SRAM1. OpenOCD will fill the
sections using data bus.
+ 0x3FFB8000 - code (OpenOCD workarea address)
+ 0x3FFBC000 - data
+ */
+ iram : org = 0x40028000, len = 0x4000
+ dram : org = 0x3FFBC000, len = 0x20000
+}
+
+INCLUDE stub_common.ld
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_chip.c
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_chip.c
new file mode 100644
index 0000000000..362f98340b
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_chip.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ * ESP32-S2 specific flasher stub functions *
+ * Copyright (C) 2021 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <ale...@espressif.com> *
+ ***************************************************************************/
+#include <string.h>
+#include "sdkconfig.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/rtc.h"
+#include "soc/efuse_periph.h"
+#include "soc/gpio_reg.h"
+#include "soc/mmu.h"
+#include "soc/extmem_reg.h"
+#include "esp_spi_flash.h"
+#include "esp32s2/spiram.h"
+#include "soc/system_reg.h"
+#include "rtc_clk_common.h"
+#include "soc/dport_access.h"
+#include "stub_rom_chip.h"
+#include "stub_logger.h"
+#include "stub_flasher_int.h"
+#include "stub_flasher_chip.h"
+#include "stub_xtensa_chips.h"
+
+uint32_t g_stub_cpu_freq_hz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * MHZ;
+
+/* Cache MMU related definitions */
+#define STUB_CACHE_BUS EXTMEM_PRO_ICACHE_MASK_DROM0
+#define STUB_MMU_DROM_VADDR SOC_MMU_VADDR0_START_ADDR
+#define STUB_MMU_DROM_PAGES_START SOC_MMU_DROM0_PAGES_START /* 128
*/
+#define STUB_MMU_DROM_PAGES_END SOC_MMU_DROM0_PAGES_END
/* 192 */
+#define STUB_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
+#define STUB_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL /* 0x400 */
+
+/* SPI Flash map request data */
+struct spiflash_map_req {
+ /* Request mapping SPI Flash base address */
+ uint32_t src_addr;
+ /* Request mapping SPI Flash size */
+ uint32_t size;
+ /* Mapped memory pointer */
+ void *ptr;
+ /* Mapped started MMU page index */
+ uint32_t start_page;
+ /* Mapped MMU page count */
+ uint32_t page_cnt;
+};
+
+extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
+
+void vPortEnterCritical(void *mux)
+{
+}
+
+void vPortExitCritical(void *mux)
+{
+}
+
+#if STUB_LOG_ENABLE == 1
+void stub_print_cache_mmu_registers(void)
+{
+ uint32_t icache_ctrl_reg = REG_READ(EXTMEM_PRO_ICACHE_CTRL_REG);
+ uint32_t icache_ctrl1_reg = REG_READ(EXTMEM_PRO_ICACHE_CTRL1_REG);
+ uint32_t dbg_status0_reg = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
+ uint32_t dbg_status1_reg = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
+
+ STUB_LOGD("icache_ctrl_reg: 0x%x icache_ctrl1_reg: 0x%x "
+ "dbg_status0_reg: 0x%x dbg_status1_reg: 0x%x\n",
+ icache_ctrl_reg,
+ icache_ctrl1_reg,
+ dbg_status0_reg,
+ dbg_status1_reg);
+}
+#endif
+
+uint32_t stub_flash_get_id(void)
+{
+ uint32_t ret;
+
+ STUB_LOGD("flash %x, cs %x, bs %x, ss %x, ps %x, sm %x\n",
+ g_rom_spiflash_chip.device_id,
+ g_rom_spiflash_chip.chip_size,
+ g_rom_spiflash_chip.block_size,
+ g_rom_spiflash_chip.sector_size,
+ g_rom_spiflash_chip.page_size,
+ g_rom_spiflash_chip.status_mask);
+
+ if (g_rom_spiflash_dummy_len_plus[1] == 0) {
+ REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
+ } else {
+ REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY);
+ REG_WRITE(PERIPHS_SPI_FLASH_USRREG1,
+ (g_rom_spiflash_dummy_len_plus[1] - 1) <<
SPI_MEM_USR_DUMMY_CYCLELEN_S);
+ }
+ WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0, 0);/* clear regisrter */
+ WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_RDID);
+ while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0)
+ ;
+ ret = READ_PERI_REG(PERIPHS_SPI_FLASH_C0) & 0xffffff;
+ STUB_LOGD("Flash ID read %x\n", ret);
+ return ret >> 16;
+}
+
+void stub_flash_cache_flush(void)
+{
+ /* we do not know breakpoint program address here, so pass wrong addr
to invalidate the
+ * whole ICache */
+ Cache_Invalidate_ICache_Items(0, 4 * 1024 * 1024);
+}
+
+void stub_cache_init(void)
+{
+ STUB_LOGD("%s\n", __func__);
+
+ Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW,
+ CACHE_MEMORY_INVALID,
+ CACHE_MEMORY_INVALID,
+ CACHE_MEMORY_INVALID);
+ Cache_Suspend_ICache();
+ Cache_Set_ICache_Mode(CACHE_SIZE_8KB, CACHE_4WAYS_ASSOC,
CACHE_LINE_SIZE_32B);
+ Cache_Invalidate_ICache_All();
+ Cache_MMU_Init();
+ REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, STUB_CACHE_BUS);
+ Cache_Resume_ICache(0);
+}
+
+bool stub_is_cache_enabled(void)
+{
+ bool is_enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG,
EXTMEM_PRO_ICACHE_ENABLE) != 0;
+ int cache_bus = REG_READ(EXTMEM_PRO_ICACHE_CTRL1_REG);
+ return is_enabled && !(cache_bus & STUB_CACHE_BUS);
+}
+
+void stub_flash_state_prepare(struct stub_flash_state *state)
+{
+ uint32_t spiconfig = ets_efuse_get_spiconfig();
+ uint32_t strapping = REG_READ(GPIO_STRAP_REG);
+ /* If GPIO1 (U0TXD) is pulled low and flash pin configuration is not
set in efuse, assume
+ * HSPI flash mode (same as normal boot) */
+ if (spiconfig == 0 && (strapping & 0x1c) == 0x08)
+ spiconfig = 1; /* HSPI flash mode */
+
+ state->cache_enabled = stub_is_cache_enabled();
+ if (!state->cache_enabled) {
+ STUB_LOGI("Cache needs to be enabled\n");
+ stub_cache_init();
+ }
+
+ /* Attach flash only if it has not been attached yet. Re-attaching it
breaks PSRAM operation. */
+ if ((READ_PERI_REG(SPI_MEM_CACHE_FCTRL_REG(0)) &
SPI_MEM_CACHE_FLASH_USR_CMD) == 0) {
+ STUB_LOGI("Attach spi flash...\n");
+ esp_rom_spiflash_attach(spiconfig, 0);
+ }
+}
+
+void stub_flash_state_restore(struct stub_flash_state *state)
+{
+ /* we do not disable or store the cache settings. So, nothing to
restore*/
+}
+
+#define RTC_PLL_FREQ_320M 320
+#define RTC_PLL_FREQ_480M 480
+
+rtc_xtal_freq_t stub_rtc_clk_xtal_freq_get(void)
+{
+ uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
+ if (!clk_val_is_valid(xtal_freq_reg)) {
+ /* invalid RTC_XTAL_FREQ_REG */
+ return RTC_XTAL_FREQ_40M;
+ }
+ return reg_val_to_clk_val(xtal_freq_reg);
+}
+
+/* Obviously we can call rtc_clk_cpu_freq_get_config() from esp-idf
+But this call may cause undesired locks due to ets_printf or abort
+*/
+int stub_rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+{
+ rtc_cpu_freq_src_t source;
+ uint32_t source_freq_mhz;
+ uint32_t div;
+ uint32_t freq_mhz;
+ uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG,
DPORT_SOC_CLK_SEL);
+ switch (soc_clk_sel) {
+ case DPORT_SOC_CLK_SEL_XTAL: {
+ source = RTC_CPU_FREQ_SRC_XTAL;
+ div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) +
1;
+ source_freq_mhz = (uint32_t)stub_rtc_clk_xtal_freq_get();
+ freq_mhz = source_freq_mhz / div;
+ }
+ break;
+ case DPORT_SOC_CLK_SEL_PLL: {
+ source = RTC_CPU_FREQ_SRC_PLL;
+ uint32_t cpuperiod_sel =
DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG,
+ DPORT_CPUPERIOD_SEL);
+ uint32_t pllfreq_sel =
DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG,
+ DPORT_PLL_FREQ_SEL);
+ source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M :
RTC_PLL_FREQ_320M;
+ if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
+ div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4;
+ freq_mhz = 80;
+ } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
+ div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2;
+ div = 3;
+ freq_mhz = 160;
+ } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
+ div = 2;
+ freq_mhz = 240;
+ } else {
+ /* unsupported frequency configuration */
+ return -1;
+ }
+ break;
+ }
+ case DPORT_SOC_CLK_SEL_8M:
+ source = RTC_CPU_FREQ_SRC_8M;
+ source_freq_mhz = 8;
+ div = 1;
+ freq_mhz = source_freq_mhz;
+ break;
+ case DPORT_SOC_CLK_SEL_APLL:
+ default:
+ /* unsupported frequency configuration */
+ return -2;
+ }
+ *out_config = (rtc_cpu_freq_config_t) {
+ .source = source,
+ .source_freq_mhz = source_freq_mhz,
+ .div = div,
+ .freq_mhz = freq_mhz
+ };
+
+ return 0;
+}
+
+int stub_cpu_clock_configure(int cpu_freq_mhz)
+{
+ rtc_cpu_freq_config_t old_config;
+ int ret = stub_rtc_clk_cpu_freq_get_config(&old_config);
+ if (ret < 0) {
+ /* this return value will avoid undesired restore requests for
unsupported frequency
+ *configuration */
+ old_config.freq_mhz = 0;
+ }
+
+#if STUB_LOG_ENABLE == 1
+ if (stub_get_log_dest() == STUB_LOG_DEST_UART)
+ uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+#endif
+
+ /* set to maximum possible value */
+ if (cpu_freq_mhz == -1)
+ cpu_freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ;
+
+ /* Set CPU to configured value. Keep other clocks unmodified. */
+ if (cpu_freq_mhz > 0) {
+ rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
+ /* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz.
+ So using default value is fine */
+ clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
+ clk_cfg.slow_freq = rtc_clk_slow_freq_get();
+ clk_cfg.fast_freq = rtc_clk_fast_freq_get();
+ rtc_clk_init(clk_cfg);
+
+ g_stub_cpu_freq_hz = cpu_freq_mhz * MHZ;
+ }
+
+ return old_config.freq_mhz;
+}
+
+#if STUB_LOG_ENABLE == 1
+void stub_uart_console_configure(int dest)
+{
+ uartAttach(NULL);
+ ets_install_uart_printf();
+ /* Set configured UART console baud rate */
+ uart_div_modify(CONFIG_CONSOLE_UART_NUM,
+ (rtc_clk_apb_freq_get() << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
+}
+#endif
+
+uint32_t stub_esp_clk_cpu_freq(void)
+{
+ return g_stub_cpu_freq_hz;
+}
+
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr,
uint32_t area_len)
+{
+ int32_t total_sector_num;
+ int32_t head_sector_num;
+ uint32_t sector_no;
+ uint32_t sector_num_per_block;
+
+ /* set read mode to Fastmode ,not QDIO mode for erase
+ *
+ * TODO: this is probably a bug as it doesn't re-enable QIO mode, not
serious as this
+ * function is not used in IDF.
+ * esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE); */
+
+ /* check if area is oversize of flash */
+ if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+
+ /* start_addr is aligned as sector boundary */
+ if (0 != (start_addr % g_rom_spiflash_chip.sector_size))
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+
+ /* Unlock flash to enable erase */
+ if (esp_rom_spiflash_unlock(/*&g_rom_spiflash_chip*/) !=
ESP_ROM_SPIFLASH_RESULT_OK)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+
+ sector_no = start_addr / g_rom_spiflash_chip.sector_size;
+ sector_num_per_block = g_rom_spiflash_chip.block_size /
g_rom_spiflash_chip.sector_size;
+ total_sector_num = (0 == (area_len % g_rom_spiflash_chip.sector_size))
? area_len /
+ g_rom_spiflash_chip.sector_size : 1 + (area_len /
g_rom_spiflash_chip.sector_size);
+
+ /* check if erase area reach over block boundary */
+ head_sector_num = sector_num_per_block - (sector_no %
sector_num_per_block);
+
+ head_sector_num =
+ (head_sector_num >= total_sector_num) ? total_sector_num :
head_sector_num;
+
+ /* JJJ, BUG of 6.0 erase
+ * middle part of area is aligned by blocks */
+ total_sector_num -= head_sector_num;
+
+ /* head part of area is erased */
+ while (head_sector_num > 0) {
+ if (esp_rom_spiflash_erase_sector(sector_no) !=
ESP_ROM_SPIFLASH_RESULT_OK)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+ sector_no++;
+ head_sector_num--;
+ }
+ while (total_sector_num > sector_num_per_block) {
+ if (ESP_ROM_SPIFLASH_RESULT_OK !=
+ esp_rom_spiflash_erase_block(sector_no /
sector_num_per_block))
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+ sector_no += sector_num_per_block;
+ total_sector_num -= sector_num_per_block;
+ }
+
+ /* tail part of area burn */
+ while (total_sector_num > 0) {
+ if (esp_rom_spiflash_erase_sector(sector_no) !=
ESP_ROM_SPIFLASH_RESULT_OK)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+ sector_no++;
+ total_sector_num--;
+ }
+
+ return ESP_ROM_SPIFLASH_RESULT_OK;
+}
+
+static inline bool esp_flash_encryption_enabled(void)
+{
+ uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG,
+ EFUSE_SPI_BOOT_CRYPT_CNT);
+
+ /* __builtin_parity is in flash, so we calculate parity inline */
+ bool enabled = false;
+ while (flash_crypt_cnt) {
+ if (flash_crypt_cnt & 1)
+ enabled = !enabled;
+ flash_crypt_cnt >>= 1;
+ }
+ return enabled;
+}
+
+esp_flash_enc_mode_t stub_get_flash_encryption_mode(void)
+{
+ static esp_flash_enc_mode_t mode = ESP_FLASH_ENC_MODE_DEVELOPMENT;
+ static bool first = true;
+
+ if (first) {
+ if (esp_flash_encryption_enabled()) {
+ /* Check if SPI_BOOT_CRYPT_CNT is write protected */
+ bool flash_crypt_cnt_wr_dis =
REG_READ(EFUSE_RD_WR_DIS_REG) &
+ EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT;
+ if (!flash_crypt_cnt_wr_dis) {
+ uint8_t flash_crypt_cnt =
REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG,
+ EFUSE_SPI_BOOT_CRYPT_CNT);
+ /* Check if SPI_BOOT_CRYPT_CNT set for
permanent encryption */
+ if (flash_crypt_cnt ==
EFUSE_SPI_BOOT_CRYPT_CNT_V)
+ flash_crypt_cnt_wr_dis = true;
+ }
+
+ if (flash_crypt_cnt_wr_dis) {
+ uint8_t dis_dl_enc =
REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG,
+ EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+ uint8_t dis_dl_icache =
REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG,
+ EFUSE_DIS_DOWNLOAD_ICACHE);
+ uint8_t dis_dl_dcache =
REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG,
+ EFUSE_DIS_DOWNLOAD_DCACHE);
+ if (dis_dl_enc && dis_dl_icache &&
dis_dl_dcache)
+ mode = ESP_FLASH_ENC_MODE_RELEASE;
+ }
+ } else {
+ mode = ESP_FLASH_ENC_MODE_DISABLED;
+ }
+ first = false;
+ STUB_LOGD("flash_encryption_mode: %d\n", mode);
+ }
+
+ return mode;
+}
+
+static int stub_flash_mmap(struct spiflash_map_req *req)
+{
+ uint32_t map_src = req->src_addr & (~(SPI_FLASH_MMU_PAGE_SIZE - 1));
+ uint32_t map_size = req->size + (req->src_addr - map_src);
+ uint32_t flash_page = map_src / SPI_FLASH_MMU_PAGE_SIZE;
+ uint32_t page_cnt = (map_size + SPI_FLASH_MMU_PAGE_SIZE - 1) /
SPI_FLASH_MMU_PAGE_SIZE;
+ int start_page, ret = ESP_ROM_SPIFLASH_RESULT_ERR;
+ uint32_t saved_state = Cache_Suspend_ICache();
+
+ for (start_page = STUB_MMU_DROM_PAGES_START; start_page <
STUB_MMU_DROM_PAGES_END;
+ ++start_page) {
+ if (STUB_MMU_TABLE[start_page] == STUB_MMU_INVALID_ENTRY_VAL)
+ break;
+ }
+
+ if (start_page + page_cnt < STUB_MMU_DROM_PAGES_END) {
+ for (int i = 0; i < page_cnt; i++)
+ STUB_MMU_TABLE[start_page + i] =
SOC_MMU_PAGE_IN_FLASH(flash_page + i);
+
+ req->start_page = start_page;
+ req->page_cnt = page_cnt;
+ req->ptr = (void *)(STUB_MMU_DROM_VADDR +
+ (start_page - STUB_MMU_DROM_PAGES_START) *
SPI_FLASH_MMU_PAGE_SIZE +
+ (req->src_addr - map_src));
+ Cache_Invalidate_Addr((uint32_t)(STUB_MMU_DROM_VADDR +
+ (start_page - STUB_MMU_DROM_PAGES_START) *
SPI_FLASH_MMU_PAGE_SIZE),
+ page_cnt * SPI_FLASH_MMU_PAGE_SIZE);
+ ret = ESP_ROM_SPIFLASH_RESULT_OK;
+ }
+
+ STUB_LOGD("start_page: %d map_src: %x map_size: %x page_cnt: %d
flash_page: %d map_ptr: %x\n",
+ start_page,
+ map_src,
+ map_size,
+ page_cnt,
+ flash_page,
+ req->ptr);
+
+ Cache_Resume_ICache(saved_state);
+
+ return ret;
+}
+
+static void stub_flash_ummap(const struct spiflash_map_req *req)
+{
+ uint32_t saved_state = Cache_Suspend_ICache();
+
+ for (int i = req->start_page; i < req->start_page + req->page_cnt; ++i)
+ STUB_MMU_TABLE[i] = STUB_MMU_INVALID_ENTRY_VAL;
+
+ Cache_Resume_ICache(saved_state);
+}
+
+int stub_flash_read_buff(uint32_t addr, void *buffer, uint32_t size)
+{
+ struct spiflash_map_req req = {
+ .src_addr = addr,
+ .size = size,
+ };
+
+ int ret = stub_flash_mmap(&req);
+
+ if (ret)
+ return ret;
+
+ memcpy(buffer, req.ptr, size);
+
+ stub_flash_ummap(&req);
+
+ return ESP_ROM_SPIFLASH_RESULT_OK;
+}
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_chip.h
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_chip.h
new file mode 100644
index 0000000000..4038924562
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_chip.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * ESP32-S2 flasher stub definitions *
+ * Copyright (C) 2021 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <ale...@espressif.com> *
+ ***************************************************************************/
+#ifndef ESP32_S2_FLASHER_STUB_H
+#define ESP32_S2_FLASHER_STUB_H
+
+#include <stdint.h>
+
+#define STUB_FLASH_SECTOR_SIZE 4096
+/* Flash geometry constants */
+#define STUB_FLASH_BLOCK_SIZE 65536
+#define STUB_FLASH_PAGE_SIZE 256
+#define STUB_FLASH_STATUS_MASK 0xFFFF
+
+struct stub_flash_state {
+ uint32_t cache_flags[2];
+ bool cache_enabled;
+};
+void stub_flash_state_prepare(struct stub_flash_state *state);
+void stub_flash_state_restore(struct stub_flash_state *state);
+
+uint32_t stub_esp_clk_cpu_freq(void);
+
+#include "stub_xtensa_chips.h"
+
+#endif /*ESP32_S2_FLASHER_STUB_H */
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_code.inc
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_code.inc
new file mode 100644
index 0000000000..5aea6b7a57
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_code.inc
@@ -0,0 +1,491 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x04,0xc3,0xfb,0x3f,0xec,0xc2,0xfb,0x3f,0x36,0x41,0x00,0x81,0xfd,0xff,0xbd,0x02,
+0x82,0x08,0x00,0xcd,0x03,0x8c,0xf8,0x91,0xfb,0xff,0x88,0x29,0x8c,0x88,0x88,0x58,
+0x8c,0x48,0xa2,0x29,0x03,0xe0,0x08,0x00,0x1d,0xf0,0x00,0x00,0x74,0xc0,0xfb,0x3f,
+0x34,0xa0,0x41,0x3f,0x2c,0xa0,0x41,0x3f,0x30,0xa0,0x41,0x3f,0x70,0xc0,0xfb,0x3f,
+0x36,0x41,0x00,0xb1,0xfa,0xff,0x82,0x0b,0x00,0x16,0xe8,0x06,0x81,0xf9,0xff,0x0c,
+0x1a,0xc0,0x20,0x00,0x98,0x08,0x0c,0x08,0x90,0x92,0x25,0x46,0x03,0x00,0x00,0x00,
+0x07,0x69,0x05,0xa0,0x88,0x30,0x80,0x80,0x74,0x90,0x91,0x41,0x56,0x09,0xff,0xc1,
+0xf3,0xff,0xbc,0xe8,0x81,0xf0,0xff,0xc0,0x20,0x00,0x88,0x08,0x47,0xe8,0x0d,0x81,
+0xec,0xff,0xc0,0x20,0x00,0x88,0x08,0x80,0x82,0x25,0x66,0x78,0x28,0x91,0xea,0xff,
+0xc0,0x20,0x00,0x88,0x09,0xc0,0x20,0x00,0xa8,0x09,0xc0,0x20,0x00,0x92,0x29,0x00,
+0x80,0x83,0xc5,0xa0,0xaa,0x41,0xa0,0x88,0x10,0x90,0x9b,0x41,0x90,0x88,0x10,0x07,
+0x68,0x03,0x0c,0x28,0x89,0x0c,0x0c,0x08,0x82,0x4b,0x00,0x81,0xe0,0xff,0x28,0x08,
+0x1d,0xf0,0x00,0x00,0x54,0xfd,0xff,0x3f,0x18,0x20,0x40,0x3f,0xff,0xff,0xff,0xdf,
+0x00,0x00,0x00,0x20,0x1c,0x20,0x40,0x3f,0x58,0x20,0x40,0x3f,0x00,0x20,0x40,0x3f,
+0x00,0x00,0x00,0x10,0x36,0x41,0x00,0xa1,0xf7,0xff,0x81,0xf7,0xff,0x22,0x0a,0x01,
+0xc0,0x20,0x00,0x98,0x08,0xcc,0xc2,0x21,0xf5,0xff,0x20,0x99,0x10,0xc0,0x20,0x00,
+0x99,0x08,0xc6,0x05,0x00,0x21,0xf2,0xff,0x20,0x99,0x20,0xc0,0x20,0x00,0x99,0x08,
+0x82,0x0a,0x01,0x21,0xf0,0xff,0x0b,0x88,0xc0,0x20,0x00,0x89,0x02,0x81,0xee,0xff,
+0x0c,0x02,0xc0,0x20,0x00,0x22,0x68,0x00,0x91,0xed,0xff,0x21,0xed,0xff,0xc0,0x20,
+0x00,0x22,0x69,0x00,0xc0,0x20,0x00,0x28,0x09,0x56,0x72,0xff,0xc0,0x20,0x00,0x28,
+0x08,0x20,0x20,0x75,0x1d,0xf0,0x00,0x00,0x48,0xe0,0x00,0x60,0x0f,0x00,0xfe,0xff,
+0x00,0xc4,0x01,0x00,0x44,0xe0,0x00,0x60,0x00,0xff,0x7f,0x00,0x90,0x60,0x42,0x3f,
+0x00,0x00,0x04,0x00,0xff,0xbf,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xfb,0xff,
+0xff,0xff,0xbf,0xff,0x36,0x41,0x00,0x91,0xf4,0xff,0xa1,0xf4,0xff,0xc0,0x20,0x00,
+0x88,0x09,0xb1,0xf7,0xff,0xa0,0x88,0x10,0xa1,0xf2,0xff,0xa0,0x88,0x20,0xc0,0x20,
+0x00,0x89,0x09,0x81,0xf0,0xff,0xa1,0xf0,0xff,0xc0,0x20,0x00,0x98,0x08,0xa0,0x99,
+0x20,0xa1,0xee,0xff,0xc0,0x20,0x00,0x99,0x08,0xc0,0x20,0x00,0x98,0x0a,0xb0,0x99,
+0x20,0xc0,0x20,0x00,0x99,0x0a,0x92,0xa0,0x66,0x97,0x12,0x23,0x27,0x39,0x08,0x92,
+0xa0,0x61,0x97,0x12,0x32,0xc6,0x0f,0x00,0x92,0xa0,0x69,0x97,0x12,0x1d,0x92,0xa0,
+0x6d,0x97,0x92,0x33,0xc0,0x20,0x00,0x28,0x08,0x91,0xe2,0xff,0x06,0x08,0x00,0x00,
+0xc0,0x20,0x00,0x28,0x08,0x91,0xe0,0xff,0x06,0x05,0x00,0x00,0xc0,0x20,0x00,0x28,
+0x08,0x91,0xde,0xff,0x06,0x02,0x00,0x00,0xc0,0x20,0x00,0x28,0x08,0x91,0xdc,0xff,
+0x90,0x22,0x10,0xc0,0x20,0x00,0x29,0x08,0x1d,0xf0,0x00,0x00,0x00,0xe0,0x00,0x60,
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+0x80,0x83,0x11,0xb1,0xf6,0xff,0x20,0x28,0x20,0x31,0xf5,0xff,0xc0,0x20,0x00,0x29,
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+0x0b,0xc0,0x20,0x00,0x38,0x04,0x27,0x83,0xf7,0x1d,0xf0,0x00,0x36,0x41,0x00,0xad,
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+0x40,0x33,0x20,0x41,0xd2,0xff,0x20,0x33,0x20,0x21,0xd1,0xff,0xc0,0x20,0x00,0x39,
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+0xff,0xc7,0xff,0xff,0x00,0x10,0x00,0x00,0x00,0x20,0x00,0x00,0x36,0x41,0x00,0x81,
+0xf7,0xff,0xb2,0xac,0x00,0xc0,0x20,0x00,0xa8,0x08,0x0b,0x33,0xb0,0xaa,0x10,0xc0,
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+0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x90,0xaa,0x01,0x40,0x36,0x41,0x00,0x81,
+0xfe,0xff,0xe0,0x08,0x00,0x81,0xf8,0xff,0x91,0xf9,0xff,0x88,0x08,0x90,0x88,0xa2,
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+0x99,0x32,0x89,0x22,0x91,0xf4,0xff,0x81,0xf3,0xff,0xa9,0x02,0x89,0x42,0x99,0x52,
+0x1d,0xf0,0x00,0x00,0x36,0x81,0x00,0x21,0xba,0xfe,0xa2,0xa1,0x03,0x22,0x02,0x00,
+0x9c,0xc2,0x21,0xb8,0xfe,0xa2,0xa1,0x06,0x88,0x22,0x9c,0x28,0x88,0x48,0x8c,0xe8,
+0xad,0x01,0xa5,0xfa,0xff,0x88,0x22,0xa8,0x32,0x88,0x48,0xbd,0x01,0xe0,0x08,0x00,
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+0xa2,0xa1,0x03,0x32,0x03,0x00,0x16,0x03,0x02,0x31,0xaa,0xfe,0xa2,0xa1,0x06,0x82,
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+0x33,0x88,0x28,0xcd,0x01,0xbd,0x02,0xe0,0x08,0x00,0x2d,0x0a,0x1d,0xf0,0x00,0x00,
+0x36,0x81,0x00,0xad,0x02,0xac,0x72,0x31,0x9e,0xfe,0x32,0x03,0x00,0xad,0x03,0x9c,
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+0xa5,0xf3,0xff,0x88,0x23,0xa8,0x33,0x88,0x18,0xcd,0x01,0xbd,0x02,0xe0,0x08,0x00,
+0x2d,0x0a,0x1d,0xf0,0x36,0x81,0x00,0xa2,0xa1,0x02,0x16,0xc2,0x02,0x31,0x90,0xfe,
+0xa2,0xa1,0x03,0x32,0x03,0x00,0x16,0x03,0x02,0x31,0x8e,0xfe,0xa2,0xa1,0x06,0x82,
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+0x44,0x10,0x51,0x91,0xfd,0x82,0x21,0x1a,0x50,0x56,0x10,0x50,0x44,0x20,0xc0,0x20,
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+0xfd,0x30,0x32,0x20,0x21,0x59,0xfd,0xa2,0xa1,0x2c,0xc0,0x20,0x00,0x39,0x02,0x81,
+0x8a,0xfd,0xe0,0x08,0x00,0x92,0x21,0x19,0x21,0x37,0xf9,0x31,0xaf,0xf9,0x20,0x29,
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+0xf6,0x47,0x02,0x86,0xe9,0xfd,0x06,0x1e,0xfe,0x1d,0xf0,0x00,0x36,0x41,0x00,0x22,
+0x02,0x00,0x92,0xa1,0x03,0x20,0x20,0x04,0x0c,0x08,0x20,0x89,0x83,0x2d,0x08,0x1d,
+0xf0,0x00,0x00,0x00,0x36,0x41,0x00,0x82,0x02,0x00,0x07,0x68,0x17,0xc0,0x20,0x00,
+0x49,0xb2,0xc0,0x20,0x00,0x49,0xa2,0x0c,0x08,0xc0,0x20,0x00,0x89,0xc2,0x39,0x92,
+0xc0,0x20,0x00,0x89,0xd2,0x1d,0xf0,0x00,0x36,0x41,0x00,0x82,0x02,0x00,0x22,0xa1,
+0x03,0x07,0x68,0x0b,0x32,0xc3,0xfc,0x22,0x13,0x00,0x22,0x53,0x01,0x22,0xa0,0x00,
+0x1d,0xf0,
+
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_code_wlog.inc
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_code_wlog.inc
new file mode 100644
index 0000000000..40026ebdb8
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_code_wlog.inc
@@ -0,0 +1,691 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0xcc,0xe1,0xfb,0x3f,0xb4,0xe1,0xfb,0x3f,0x36,0x41,0x00,0x81,0xfd,0xff,0xbd,0x02,
+0x82,0x08,0x00,0xcd,0x03,0x8c,0xf8,0x91,0xfb,0xff,0x88,0x29,0x8c,0x88,0x88,0x58,
+0x8c,0x48,0xa2,0x29,0x03,0xe0,0x08,0x00,0x1d,0xf0,0x00,0x00,0xb0,0xd1,0xfb,0x3f,
+0x36,0x41,0x00,0x91,0xfe,0xff,0x88,0x09,0x8a,0xa9,0x1b,0x88,0x80,0x80,0xb4,0x22,
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+0x00,0xc4,0x01,0x00,0x44,0xe0,0x00,0x60,0x00,0xff,0x7f,0x00,0x90,0x60,0x42,0x3f,
+0x00,0x00,0x04,0x00,0xff,0xbf,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xfb,0xff,
+0xff,0xff,0xbf,0xff,0x36,0x41,0x00,0x91,0xf4,0xff,0xa1,0xf4,0xff,0xc0,0x20,0x00,
+0x88,0x09,0xb1,0xf7,0xff,0xa0,0x88,0x10,0xa1,0xf2,0xff,0xa0,0x88,0x20,0xc0,0x20,
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diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_data.inc
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_data.inc
new file mode 100644
index 0000000000..df159e9f6b
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_data.inc
@@ -0,0 +1,34 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
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diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_data_wlog.inc
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_data_wlog.inc
new file mode 100644
index 0000000000..0dbfeb3239
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_data_wlog.inc
@@ -0,0 +1,269 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
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diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_image.h
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_image.h
new file mode 100644
index 0000000000..f7013a6fa7
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_image.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define ESP32S2_STUB_BSS_SIZE 0x000010dUL
+
+#define ESP32S2_STUB_IRAM_ORG 0x040028000UL
+
+#define ESP32S2_STUB_IRAM_LEN 0x000004000UL
+
+#define ESP32S2_STUB_DRAM_ORG 0x03ffbc000UL
+
+#define ESP32S2_STUB_DRAM_LEN 0x000020000UL
+
+#define ESP32S2_STUB_ENTRY_ADDR 0x04002942cUL
+
+#define ESP32S2_STUB_APPTRACE_CTRL_ADDR 0x0
+/*#define ESP32S2_STUB_BUILD_IDF_REV 68e5d9d585
+*/
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_flasher_image_wlog.h
b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_image_wlog.h
new file mode 100644
index 0000000000..151e05254d
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_flasher_image_wlog.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define ESP32S2_STUB_WLOG_BSS_SIZE 0x0001118UL
+
+#define ESP32S2_STUB_WLOG_LOG_ADDR 0x03ffbd1b0UL
+
+#define ESP32S2_STUB_WLOG_LOG_SIZE 4100UL
+
+#define ESP32S2_STUB_WLOG_ENTRY_ADDR 0x040029bb4UL
+
+#define ESP32S2_STUB_WLOG_APPTRACE_CTRL_ADDR 0x0
+/*#define ESP32S2_STUB_WLOG_BUILD_IDF_REV 68e5d9d585
+*/
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_rom_chip.h
b/contrib/loaders/flash/espressif/esp32s2/stub_rom_chip.h
new file mode 100644
index 0000000000..0d60066e69
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_rom_chip.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * ESP32-S2 specific rom header files *
+ * Copyright (C) 2021 Espressif Systems Ltd. *
+ * Author: Erhan Kurubas <erhan.kuru...@espressif.com> *
+ ***************************************************************************/
+#ifndef ESP_STUB_ROM_H
+#define ESP_STUB_ROM_H
+
+#include "esp32s2/rom/ets_sys.h"
+#include "esp32s2/rom/spi_flash.h"
+#include "esp32s2/rom/miniz.h"
+#include "esp32s2/rom/spi_flash.h"
+#include "esp32s2/rom/cache.h"
+#include "esp32s2/rom/efuse.h"
+#include "esp32s2/rom/uart.h"
+#include "esp32s2/rom/rtc.h"
+#include "esp32s2/rom/sha.h"
+#endif
diff --git a/contrib/loaders/flash/espressif/esp32s2/stub_sha.c
b/contrib/loaders/flash/espressif/esp32s2/stub_sha.c
new file mode 100644
index 0000000000..e81c545c26
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32s2/stub_sha.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD */
+
+#include <string.h>
+#include "stub_rom_chip.h"
+
+static SHA_CTX ctx;
+
+void stub_sha256_start(void)
+{
+ /* Enable SHA hardware */
+ ets_sha_enable();
+ ets_sha_init(&ctx, SHA2_256);
+}
+
+void stub_sha256_data(const void *data, size_t data_len)
+{
+ if (data_len % 4 != 0)
+ return;
+ ets_sha_update(&ctx, data, data_len, false);
+}
+
+void stub_sha256_finish(uint8_t *digest)
+{
+ if (!digest) {
+ bzero(&ctx, sizeof(ctx));
+ return;
+ }
+ ets_sha_finish(&ctx, digest);
+ ets_sha_disable();
+}
--
