This is an automated email from Gerrit.
"Erhan Kurubas <erhan.kuru...@espressif.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8029
-- gerrit
commit 73b56d1d391761026db6083d8b8f15fb11477d6c
Author: Erhan Kurubas <erhan.kuru...@espressif.com>
Date: Thu Nov 30 13:04:55 2023 +0100
loaders/espressif: add esp32c2 stub flasher application code
Special binary program running on the target (ESP32-C2) to perform
flash operations and communicate to the OpenOCD host.
Camelcase symbols comes from esp-idf
Checkpatch-ignore: CAMELCASE
Signed-off-by: Erhan Kurubas <erhan.kuru...@espressif.com>
Change-Id: Idb01fe91b62d3d622141d668d004b5379b081639
diff --git a/contrib/loaders/flash/espressif/esp32c2/Makefile
b/contrib/loaders/flash/espressif/esp32c2/Makefile
new file mode 100644
index 0000000000..3a6ae1eb4a
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/Makefile
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Makefile to compile flasher stub program
+# Copyright (C) 2022 Espressif Systems Ltd.
+
+# Prefix for ESP32-C2 cross compilers (can include a directory path)
+CROSS ?= riscv32-esp-elf-
+
+# Path to the esp-idf root dir
+IDF_PATH ?= ../..
+
+STUB_ARCH := riscv
+STUB_CHIP_PATH := $(shell pwd)
+STUB_COMMON_PATH := $(STUB_CHIP_PATH)/..
+STUB_CHIP_ARCH_PATH := $(STUB_COMMON_PATH)/$(STUB_ARCH)
+STUB_OBJ_DEPS := sdkconfig.h
+STUB_LD_SCRIPT := stub.ld
+STUB_CHIP := ESP32C2
+
+SRCS := $(IDF_PATH)/components/esp_hw_support/port/esp32c2/rtc_clk_init.c \
+ $(IDF_PATH)/components/esp_hw_support/port/esp32c2/rtc_clk.c \
+ $(IDF_PATH)/components/esp_hw_support/port/esp32c2/rtc_time.c \
+ $(IDF_PATH)/components/esp_hw_support/port/esp32c2/systimer.c \
+ $(IDF_PATH)/components/app_trace/port/$(STUB_ARCH)/port.c
+
+CFLAGS := -std=gnu17
+
+INCLUDES := -I$(IDF_PATH)/components/soc/esp32c2/include
-I$(IDF_PATH)/components/riscv/include \
+ -I$(IDF_PATH)/components/hal/esp32c2/include
-I$(IDF_PATH)/components/esp32c2/include \
+ -I$(IDF_PATH)/components/esp_hw_support/port/esp32c2/private_include \
+ -I$(IDF_PATH)/components/esp_rom/include/esp32c2 \
+ -I$(IDF_PATH)/components/esp_hw_support/port/esp32c2 \
+ -I$(IDF_PATH)/components/spi_flash/include \
+ -I$(IDF_PATH)/components/hal/esp32c2/include \
+ -I$(IDF_PATH)/components/esp_rom/esp32c2
+
+DEFINES :=
+
+LDFLAGS += -T$(IDF_PATH)/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
-T$(IDF_PATH)/components/esp_rom/esp32c2/ld/esp32c2.rom.newlib.ld \
+ -T$(IDF_PATH)/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
-T$(IDF_PATH)/components/soc/esp32c2/ld/esp32c2.peripherals.ld
+
+include ../stub_common.mk
diff --git a/contrib/loaders/flash/espressif/esp32c2/sdkconfig.h
b/contrib/loaders/flash/espressif/esp32c2/sdkconfig.h
new file mode 100644
index 0000000000..0be4cd7b0f
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/sdkconfig.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _STUB_SDKCONFIG_H_
+#define _STUB_SDKCONFIG_H_
+
+#define CONFIG_IDF_TARGET_ARCH_RISCV 1
+#define CONFIG_IDF_TARGET_ESP32C2 1
+#define CONFIG_FREERTOS_UNICORE 1
+/* Use ROM flash driver patch
+ * #define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
+ * Disable application module multi-threading lock */
+#define CONFIG_APPTRACE_LOCK_ENABLE 0
+/* Enable apptarce module for flash data transfers */
+#define CONFIG_APPTRACE_DEST_JTAG 1
+#define CONFIG_APPTRACE_MEMBUFS_APPTRACE_PROTO_ENABLE 1
+#define CONFIG_APPTRACE_ENABLE 1
+#define CONFIG_APPTRACE_BUF_SIZE 16384
+#define CONFIG_APPTRACE_PENDING_DATA_SIZE_MAX 0
+/* Debug UART number */
+#define CONFIG_CONSOLE_UART_NUM 0
+/* Debug UART baudrate */
+#define CONFIG_CONSOLE_UART_BAUDRATE 115200
+/* alloc apptrace data buffers on stack */
+#define CONFIG_STUB_STACK_DATA_POOL_SIZE (2 * CONFIG_APPTRACE_BUF_SIZE)
+
+/* needed due to apptrace sources usage */
+#define CONFIG_LOG_MAXIMUM_LEVEL 0
+/* needed due to various checks in IDF headers */
+#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
+/* TODO: use current clk, get it from PLL settings */
+#define CONFIG_ESP32C2_DEFAULT_CPU_FREQ_MHZ 120
+#define CONFIG_XTAL_FREQ 40
+#define CONFIG_XTAL_FREQ_40 1
+/* Unused by stub, just for compilation of IDF */
+#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
+#define CONFIG_MMU_PAGE_SIZE 0x10000 /* 64KB */
+
+#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1
+
+#endif /*_STUB_SDKCONFIG_H_ */
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub.ld
b/contrib/loaders/flash/espressif/esp32c2/stub.ld
new file mode 100644
index 0000000000..26f4b69dac
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub.ld
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * LD script for ESP32-C2 flasher stub *
+ * Copyright (C) 2021 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <ale...@espressif.com> *
+ ***************************************************************************/
+
+MEMORY {
+ /* Place sections by starting from the Internal SRAM1. OpenOCD will fill the
sections using data bus.
+ 0x3FCA0000 - code (OpenOCD workarea address)
+ 0x3FCA4000 - data
+ */
+ iram : org = 0x40380000, len = 0x4000
+ dram : org = 0x3FCA4000, len = 0x20000
+}
+
+INCLUDE stub_common.ld
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_chip.c
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_chip.c
new file mode 100644
index 0000000000..31c02e9ded
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_chip.c
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ * ESP32-C2 specific flasher stub functions *
+ * Copyright (C) 2021 Espressif Systems Ltd. *
+ ***************************************************************************/
+#include <string.h>
+#include "sdkconfig.h"
+#include "soc/rtc.h"
+#include "soc/efuse_periph.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/extmem_reg.h"
+#include "soc/gpio_reg.h"
+#include "soc/mmu.h"
+#include "soc/system_reg.h"
+#include "hal/mmu_ll.h"
+#include "hal/systimer_ll.h"
+#include "systimer.h"
+#include "esp_app_trace_membufs_proto.h"
+#include "stub_rom_chip.h"
+#include "stub_logger.h"
+#include "stub_flasher_int.h"
+#include "stub_flasher_chip.h"
+#include "stub_flasher.h"
+
+/* RTC related definitios */
+#define SYSTEM_SOC_CLK_MAX 1
+#define SYSTEM_CPUPERIOD_MAX 1 // CPU_CLK frequency is 120 MHz
+
+/* Cache MMU related definitions */
+#define STUB_CACHE_BUS EXTMEM_ICACHE_SHUT_DBUS
+#define STUB_MMU_TABLE ((volatile uint32_t
*)DR_REG_MMU_TABLE) /* 0x600c5000 */
+#define STUB_MMU_INVALID_ENTRY_VAL MMU_INVALID /*
BIT(6) */
+
+#define ESP_APPTRACE_RISCV_BLOCK_LEN_MSK 0x7FFFUL
+#define ESP_APPTRACE_RISCV_BLOCK_LEN(_l_) ((_l_) &
ESP_APPTRACE_RISCV_BLOCK_LEN_MSK)
+#define ESP_APPTRACE_RISCV_BLOCK_LEN_GET(_v_) ((_v_) &
ESP_APPTRACE_RISCV_BLOCK_LEN_MSK)
+#define ESP_APPTRACE_RISCV_BLOCK_ID_MSK 0x7FUL
+#define ESP_APPTRACE_RISCV_BLOCK_ID(_id_) (((_id_) &
ESP_APPTRACE_RISCV_BLOCK_ID_MSK) << 15)
+#define ESP_APPTRACE_RISCV_BLOCK_ID_GET(_v_) (((_v_) >> 15) &
ESP_APPTRACE_RISCV_BLOCK_ID_MSK)
+#define ESP_APPTRACE_RISCV_HOST_DATA BIT(22)
+#define ESP_APPTRACE_RISCV_HOST_CONNECT BIT(23)
+
+/** RISCV memory host iface control block */
+typedef struct {
+ uint32_t ctrl;
+ /* - Guard field. If this register is not zero then CPU is changing
this struct and */
+ /* this guard field holds address of the instruction which
application will execute when
+ * CPU finishes with those modifications. */
+ uint32_t stat;
+ esp_apptrace_mem_block_t *mem_blocks;
+} esp_apptrace_riscv_ctrl_block_t;
+
+static esp_apptrace_riscv_ctrl_block_t *s_apptrace_ctrl;
+#if CONFIG_STUB_STACK_DATA_POOL_SIZE > 0
+static uint8_t *s_stack_data_pool;
+static size_t s_stack_data_pool_sz;
+#endif
+
+typedef struct {
+ mmu_page_size_t page_size;
+ uint32_t vaddr0_start_addr;
+ uint32_t drom_page_start;
+ uint32_t drom_page_end;
+} cache_mmu_config_t;
+
+static cache_mmu_config_t s_cache_mmu_config;
+
+/* SPI Flash map request data */
+struct spiflash_map_req {
+ /* Request mapping SPI Flash base address */
+ uint32_t src_addr;
+ /* Request mapping SPI Flash size */
+ uint32_t size;
+ /* Mapped memory pointer */
+ void *ptr;
+ /* Mapped started MMU page index */
+ uint32_t start_page;
+ /* Mapped MMU page count */
+ uint32_t page_cnt;
+};
+
+static systimer_dev_t *s_sys_timer_dev = &SYSTIMER;
+static uint32_t s_sys_timer_conf;
+
+uint32_t g_stub_cpu_freq_hz = CONFIG_ESP32C2_DEFAULT_CPU_FREQ_MHZ * MHZ;
+
+void vPortEnterCritical(void)
+{
+}
+
+void vPortExitCritical(void)
+{
+}
+
+int xPortInIsrContext(void)
+{
+ return 0;
+}
+
+void *esp_apptrace_uart_hw_get(int num, void **data)
+{
+ return NULL;
+}
+
+#if STUB_LOG_ENABLE == 1
+void stub_print_cache_mmu_registers(void)
+{
+ uint32_t icache_ctrl1_reg = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
+
+ STUB_LOGD("icache_ctrl1_reg: 0x%x\n",
+ icache_ctrl1_reg);
+}
+#endif
+
+uint32_t stub_flash_get_id(void)
+{
+ uint32_t ret;
+
+ STUB_LOGD("flash %x, cs %x, bs %x, ss %x, ps %x, sm %x\n",
+ rom_spiflash_legacy_data->chip.device_id,
+ rom_spiflash_legacy_data->chip.chip_size,
+ rom_spiflash_legacy_data->chip.block_size,
+ rom_spiflash_legacy_data->chip.sector_size,
+ rom_spiflash_legacy_data->chip.page_size,
+ rom_spiflash_legacy_data->chip.status_mask);
+ WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0, 0); /* clear register */
+ WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_RDID);
+ while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0)
+ ;
+ ret = READ_PERI_REG(PERIPHS_SPI_FLASH_C0) & 0xffffff;
+ STUB_LOGD("Flash ID read %x\n", ret);
+ return ret >> 16;
+}
+
+void stub_flash_cache_flush(void)
+{
+ /* we do not know breakpoint program address here, so invalidate the
+ * whole ICache */
+ Cache_Invalidate_ICache_All();
+}
+
+void stub_cache_init(void)
+{
+ STUB_LOGD("%s\n", __func__);
+
+ Cache_Mask_All();
+ /* init cache mmu, set cache mode, invalidate cache tags, enable cache*/
+ REG_SET_BIT(SYSTEM_CACHE_CONTROL_REG, SYSTEM_ICACHE_CLK_ON);
+ REG_SET_BIT(SYSTEM_CACHE_CONTROL_REG, SYSTEM_ICACHE_RESET);
+ REG_CLR_BIT(SYSTEM_CACHE_CONTROL_REG, SYSTEM_ICACHE_RESET);
+ /* init cache owner bit */
+ Cache_Owner_Init();
+ /* set page mode */
+ mmu_ll_set_page_size(0, CONFIG_MMU_PAGE_SIZE);
+ /* clear mmu entry */
+ Cache_MMU_Init();
+ /* config cache mode */
+ Cache_Set_Default_Mode();
+ Cache_Enable_ICache(0);
+ REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, STUB_CACHE_BUS);
+}
+
+bool stub_is_cache_enabled(void)
+{
+ bool is_enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG,
EXTMEM_ICACHE_ENABLE) != 0;
+ int cache_bus = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
+ STUB_LOGD("Cache is_enabled:%d cache_bus:%X\n", is_enabled, cache_bus);
+ return is_enabled && !(cache_bus & STUB_CACHE_BUS);
+}
+
+void stub_cache_configure(void)
+{
+ s_cache_mmu_config.page_size = mmu_ll_get_page_size(0);
+
+ switch (s_cache_mmu_config.page_size) {
+ case MMU_PAGE_64KB:
+ s_cache_mmu_config.drom_page_start = 2;
+ break;
+ case MMU_PAGE_32KB:
+ s_cache_mmu_config.drom_page_start = 1;
+ break;
+ case MMU_PAGE_16KB:
+ s_cache_mmu_config.drom_page_start = 3;
+ break;
+ default:
+ STUB_LOGE("Unknown page size!");
+ return;
+ }
+
+ s_cache_mmu_config.drom_page_end = 64;
+ s_cache_mmu_config.vaddr0_start_addr =
+ (SOC_DROM_LOW + (s_cache_mmu_config.drom_page_start *
s_cache_mmu_config.page_size));
+
+ STUB_LOGI("MMU page size:%X drom_page_start:%d drom_page_end:%d
vaddr0_start_addr:%X\n",
+ s_cache_mmu_config.page_size,
+ s_cache_mmu_config.drom_page_start,
+ s_cache_mmu_config.drom_page_end,
+ s_cache_mmu_config.vaddr0_start_addr);
+}
+
+void stub_systimer_init(void)
+{
+ /* Enable APB_CLK signal if not enabled yet */
+ if (!GET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG,
SYSTEM_SYSTIMER_CLK_EN)) {
+ SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG,
SYSTEM_SYSTIMER_CLK_EN);
+ CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_SYSTIMER_RST);
+ STUB_LOGI("Systimer clock enabled\n");
+ }
+
+ s_sys_timer_conf = s_sys_timer_dev->conf.val;
+
+ /* enable SYSTIMER_LL_COUNTER_CLOCK */
+ s_sys_timer_dev->conf.clk_en = 1;
+ s_sys_timer_dev->conf.timer_unit0_work_en = 1;
+ s_sys_timer_dev->conf.timer_unit0_core0_stall_en = 0;
+}
+
+void stub_flash_state_prepare(struct stub_flash_state *state)
+{
+ const uint32_t spiconfig = 0; /* ESP32C2 doesn't support
ets_efuse_get_spiconfig(); */
+
+ state->cache_enabled = stub_is_cache_enabled();
+ if (!state->cache_enabled) {
+ STUB_LOGI("Cache needs to be enabled\n");
+ stub_cache_init();
+ }
+ stub_cache_configure();
+ stub_systimer_init();
+
+ esp_rom_spiflash_attach(spiconfig, false);
+}
+
+void stub_flash_state_restore(struct stub_flash_state *state)
+{
+ /* we do not disable or store the cache settings. So, nothing to
restore*/
+
+ /* restore timer settings */
+ s_sys_timer_dev->conf.val = s_sys_timer_conf;
+}
+
+int stub_cpu_clock_configure(int conf_reg_val)
+{
+ uint32_t sysclk_conf_reg = 0;
+
+ /* set to maximum possible value */
+ if (conf_reg_val == -1) {
+ sysclk_conf_reg = REG_READ(SYSTEM_SYSCLK_CONF_REG) & 0xFFF;
+ REG_WRITE(SYSTEM_SYSCLK_CONF_REG,
+ (sysclk_conf_reg & ~SYSTEM_SOC_CLK_SEL_M) |
(SYSTEM_SOC_CLK_MAX << SYSTEM_SOC_CLK_SEL_S));
+ } else { // restore old value
+ sysclk_conf_reg = conf_reg_val;
+ REG_WRITE(SYSTEM_SYSCLK_CONF_REG,
+ (REG_READ(SYSTEM_SYSCLK_CONF_REG) &
~SYSTEM_SOC_CLK_SEL_M) | (sysclk_conf_reg & SYSTEM_SOC_CLK_SEL_M));
+ }
+
+ STUB_LOGD("sysclk_conf_reg %x\n", sysclk_conf_reg);
+
+ return conf_reg_val;
+}
+
+#if STUB_LOG_ENABLE == 1
+void stub_uart_console_configure(int dest)
+{
+ extern bool g_uart_print;
+ /* set the default parameter to UART module, but don't enable RX
interrupt */
+ uartAttach(NULL);
+ /* first enable uart0 as printf channel */
+ uint32_t clock = ets_get_apb_freq();
+ ets_update_cpu_frequency(clock / 1000000);
+
+ Uart_Init(0, APB_CLK_FREQ_ROM);
+ /* install to print later
+ * Non-Flash Boot can print
+ * Flash Boot can print when RTC_CNTL_STORE4_REG bit0 is 0 (can be 1
after deep sleep, software reset)
+ * and printf boot.
+ * print boot determined by GPIO and efuse, see ets_is_print_boot
+ */
+ g_uart_print = true;
+ ets_install_uart_printf();
+}
+#endif
+
+uint32_t stub_esp_clk_cpu_freq(void)
+{
+ return CONFIG_ESP32C2_DEFAULT_CPU_FREQ_MHZ * 1000000;
+}
+
+/* override apptrace control block advertising func, IDF's implementation
issues syscall */
+int esp_apptrace_advertise_ctrl_block(void *ctrl_block_addr)
+{
+ s_apptrace_ctrl = ctrl_block_addr;
+ return 0;
+}
+
+#if CONFIG_STUB_STACK_DATA_POOL_SIZE > 0
+void stub_stack_data_pool_init(uint8_t *data, size_t sz)
+{
+ STUB_LOGD("stack data pool %lu bytes @ 0x%x\n", sz, data);
+ s_stack_data_pool = data;
+ s_stack_data_pool_sz = sz;
+}
+
+void esp_apptrace_get_up_buffers(esp_apptrace_mem_block_t mem_blocks_cfg[2])
+{
+ /* use whole stack data pool for apptrace up buffers */
+ mem_blocks_cfg[0].start = s_stack_data_pool;
+ mem_blocks_cfg[0].sz = s_stack_data_pool_sz / 2;
+ mem_blocks_cfg[1].start = s_stack_data_pool + mem_blocks_cfg[0].sz;
+ mem_blocks_cfg[1].sz = mem_blocks_cfg[0].sz;
+}
+#endif
+
+int stub_apptrace_prepare(void)
+{
+ /* imply that host is auto-connected */
+ s_apptrace_ctrl->ctrl |= ESP_APPTRACE_RISCV_HOST_CONNECT;
+ return ESP_STUB_ERR_OK;
+}
+
+/* this function is used for perf measurements only.*/
+uint64_t stub_get_time(void)
+{
+ uint32_t lo, lo_start, hi;
+
+ /* Set the "update" bit and wait for acknowledgment */
+ systimer_ll_counter_snapshot(s_sys_timer_dev, SYSTIMER_COUNTER_OS_TICK);
+ while (!systimer_ll_is_counter_value_valid(s_sys_timer_dev,
SYSTIMER_COUNTER_OS_TICK))
+ ;
+
+ /* Read LO, HI, then LO again, check that LO returns the same value.
+ * This accounts for the case when an interrupt may happen between
reading
+ * HI and LO values, and this function may get called from the ISR.
+ * In this case, the repeated read will return consistent values.
+ */
+ lo_start = systimer_ll_get_counter_value_low(s_sys_timer_dev,
SYSTIMER_COUNTER_OS_TICK);
+ do {
+ lo = lo_start;
+ hi = systimer_ll_get_counter_value_high(s_sys_timer_dev,
SYSTIMER_COUNTER_OS_TICK);
+ lo_start = systimer_ll_get_counter_value_low(s_sys_timer_dev,
SYSTIMER_COUNTER_OS_TICK);
+ } while (lo_start != lo);
+
+ return systimer_ticks_to_us(((uint64_t)hi << 32) | lo);
+}
+
+/* this function is used by apptrace code to implement timeouts */
+int64_t esp_timer_get_time(void)
+{
+ return (int64_t)stub_get_time();
+}
+
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr,
uint32_t area_len)
+{
+ int32_t total_sector_num;
+ int32_t head_sector_num;
+ uint32_t sector_no;
+ uint32_t sector_num_per_block;
+
+ /* set read mode to Fastmode ,not QDIO mode for erase
+ *
+ * TODO: this is probably a bug as it doesn't re-enable QIO mode, not
serious as this
+ * function is not used in IDF.
+ * esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE); */
+
+ /* check if area is oversize of flash */
+ if ((start_addr + area_len) > rom_spiflash_legacy_data->chip.chip_size)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+
+ /* start_addr is aligned as sector boundary */
+ if (0 != (start_addr % rom_spiflash_legacy_data->chip.sector_size))
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+
+ /* Unlock flash to enable erase */
+ if (esp_rom_spiflash_unlock(/*&rom_spiflash_legacy_data->chip*/) !=
ESP_ROM_SPIFLASH_RESULT_OK)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+
+ sector_no = start_addr / rom_spiflash_legacy_data->chip.sector_size;
+ sector_num_per_block = rom_spiflash_legacy_data->chip.block_size /
rom_spiflash_legacy_data->chip.sector_size;
+ total_sector_num = (0 == (area_len %
rom_spiflash_legacy_data->chip.sector_size)) ?
+ area_len / rom_spiflash_legacy_data->chip.sector_size :
+ 1 + (area_len / rom_spiflash_legacy_data->chip.sector_size);
+
+ /* check if erase area reach over block boundary */
+ head_sector_num = sector_num_per_block - (sector_no %
sector_num_per_block);
+
+ head_sector_num = (head_sector_num >= total_sector_num) ?
total_sector_num : head_sector_num;
+
+ /* JJJ, BUG of 6.0 erase
+ * middle part of area is aligned by blocks */
+ total_sector_num -= head_sector_num;
+
+ /* head part of area is erased */
+ while (head_sector_num > 0) {
+ if (esp_rom_spiflash_erase_sector(sector_no) !=
ESP_ROM_SPIFLASH_RESULT_OK)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+ sector_no++;
+ head_sector_num--;
+ }
+ while (total_sector_num > sector_num_per_block) {
+ if (ESP_ROM_SPIFLASH_RESULT_OK !=
+ esp_rom_spiflash_erase_block(sector_no /
sector_num_per_block))
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+ sector_no += sector_num_per_block;
+ total_sector_num -= sector_num_per_block;
+ }
+
+ /* tail part of area burn */
+ while (total_sector_num > 0) {
+ if (esp_rom_spiflash_erase_sector(sector_no) !=
ESP_ROM_SPIFLASH_RESULT_OK)
+ return ESP_ROM_SPIFLASH_RESULT_ERR;
+ sector_no++;
+ total_sector_num--;
+ }
+
+ return ESP_ROM_SPIFLASH_RESULT_OK;
+}
+
+static inline bool esp_flash_encryption_enabled(void)
+{
+ uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA0_REG,
EFUSE_SPI_BOOT_CRYPT_CNT);
+
+ /* __builtin_parity is in flash, so we calculate parity inline */
+ bool enabled = false;
+ while (flash_crypt_cnt) {
+ if (flash_crypt_cnt & 1)
+ enabled = !enabled;
+ flash_crypt_cnt >>= 1;
+ }
+ return enabled;
+}
+
+esp_flash_enc_mode_t stub_get_flash_encryption_mode(void)
+{
+ static esp_flash_enc_mode_t s_mode = ESP_FLASH_ENC_MODE_DEVELOPMENT;
+ static bool s_first = true;
+
+ if (s_first) {
+ if (!esp_flash_encryption_enabled())
+ s_mode = ESP_FLASH_ENC_MODE_DISABLED;
+ s_first = false;
+ STUB_LOGD("flash_encryption_mode: %d\n", s_mode);
+ }
+ return s_mode;
+}
+
+static int stub_flash_mmap(struct spiflash_map_req *req)
+{
+ uint32_t map_src = req->src_addr & (~(s_cache_mmu_config.page_size -
1));
+ uint32_t map_size = req->size + (req->src_addr - map_src);
+ uint32_t flash_page = map_src / s_cache_mmu_config.page_size;
+ uint32_t page_cnt = (map_size + s_cache_mmu_config.page_size - 1) /
s_cache_mmu_config.page_size;
+ int start_page, ret = ESP_ROM_SPIFLASH_RESULT_ERR;
+ uint32_t saved_state = Cache_Suspend_ICache() << 16;
+
+ for (start_page = s_cache_mmu_config.drom_page_start; start_page <
s_cache_mmu_config.drom_page_end;
+ ++start_page) {
+ if (STUB_MMU_TABLE[start_page] == STUB_MMU_INVALID_ENTRY_VAL)
+ break;
+ }
+
+ if (start_page == s_cache_mmu_config.drom_page_end)
+ start_page = s_cache_mmu_config.drom_page_start;
+
+ if (start_page + page_cnt < s_cache_mmu_config.drom_page_end) {
+ for (int i = 0; i < page_cnt; i++)
+ STUB_MMU_TABLE[start_page + i] =
SOC_MMU_PAGE_IN_FLASH(flash_page + i);
+
+ req->start_page = start_page;
+ req->page_cnt = page_cnt;
+ req->ptr = (void *)(s_cache_mmu_config.vaddr0_start_addr +
+ (start_page - s_cache_mmu_config.drom_page_start) *
s_cache_mmu_config.page_size +
+ (req->src_addr - map_src));
+
Cache_Invalidate_Addr((uint32_t)(s_cache_mmu_config.vaddr0_start_addr +
+ (start_page -
s_cache_mmu_config.drom_page_start) * s_cache_mmu_config.page_size),
+ page_cnt * s_cache_mmu_config.page_size);
+ ret = ESP_ROM_SPIFLASH_RESULT_OK;
+ }
+
+ STUB_LOGD("start_page: %d map_src: %x map_size: %x page_cnt: %d
flash_page: %d map_ptr: %x\n",
+ start_page,
+ map_src,
+ map_size,
+ page_cnt,
+ flash_page,
+ req->ptr);
+
+ Cache_Resume_ICache(saved_state >> 16);
+
+ return ret;
+}
+
+static void stub_flash_ummap(const struct spiflash_map_req *req)
+{
+ uint32_t saved_state = Cache_Suspend_ICache() << 16;
+
+ for (int i = req->start_page; i < req->start_page + req->page_cnt; ++i)
+ STUB_MMU_TABLE[i] = STUB_MMU_INVALID_ENTRY_VAL;
+
+ Cache_Resume_ICache(saved_state >> 16);
+}
+
+int stub_flash_read_buff(uint32_t addr, void *buffer, uint32_t size)
+{
+ struct spiflash_map_req req = {
+ .src_addr = addr,
+ .size = size,
+ };
+
+ int ret = stub_flash_mmap(&req);
+
+ if (ret)
+ return ret;
+
+ memcpy(buffer, req.ptr, size);
+
+ stub_flash_ummap(&req);
+
+ return ESP_ROM_SPIFLASH_RESULT_OK;
+}
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_chip.h
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_chip.h
new file mode 100644
index 0000000000..2fe4ffb34c
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_chip.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * ESP32-C2 flasher stub definitions *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <ale...@espressif.com> *
+ ***************************************************************************/
+#ifndef ESP32C2_FLASHER_STUB_H
+#define ESP32C2_FLASHER_STUB_H
+
+#include "sdkconfig.h"
+
+#define STUB_FLASH_SECTOR_SIZE 0x1000
+/* Flash geometry constants */
+#define STUB_FLASH_BLOCK_SIZE 0x10000
+#define STUB_FLASH_PAGE_SIZE 0x100
+#define STUB_FLASH_STATUS_MASK 0xFFFF
+
+struct stub_flash_state {
+ uint32_t cache_flags[2];
+ bool cache_enabled;
+};
+
+#define ESP_APPTRACE_USR_DATA_LEN_MAX (CONFIG_APPTRACE_BUF_SIZE - 2)
+#define RISCV_EBREAK 0x9002
+
+extern bool ets_efuse_flash_octal_mode(void);
+
+uint32_t stub_esp_clk_cpu_freq(void);
+
+static inline uint8_t stub_get_insn_size(uint8_t *insn)
+{
+ /* we use 16bit `c.ebreak`. it works perfectly with either 32bit and
16bit code */
+ return 2;
+}
+
+static inline uint32_t stub_get_break_insn(uint8_t insn_sz)
+{
+ return RISCV_EBREAK;
+}
+
+void stub_stack_data_pool_init(uint8_t *data, size_t sz);
+
+#endif /*ESP32C2_FLASHER_STUB_H */
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_code.inc
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_code.inc
new file mode 100644
index 0000000000..a30955e935
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_code.inc
@@ -0,0 +1,334 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x83,0x47,0x05,0x00,0x85,0x8b,0x99,0xc7,0x83,0xd7,0xc5,0xff,0x01,0x45,0x23,0x9f,
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+0xb5,0xbf,0x69,0x54,0x21,0xb7,0x65,0x54,0x11,0xb7,0x7d,0x7b,0x97,0xf0,0xc7,0xff,
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+0x26,0x85,0xef,0xf0,0x8f,0xbe,0x79,0xfd,0x89,0x47,0x23,0x00,0xf4,0x00,0x93,0x07,
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+0x33,0xfb,0x64,0x01,0x09,0x66,0xce,0x85,0x5a,0x85,0xef,0xf0,0x4f,0xc9,0xe3,0x16,
+0x05,0xec,0x89,0x45,0x26,0x85,0xef,0xf0,0x4f,0xb9,0x2a,0x84,0xe3,0x1f,0x05,0xea,
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+0x19,0x00,0xa3,0x80,0xf4,0x00,0xef,0xe0,0xdf,0xce,0xb3,0x36,0xa0,0x00,0x09,0x66,
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+0x0c,0x60,0x3c,0x4f,0x93,0xf7,0xf7,0x3f,0x93,0xe7,0x07,0x40,0x3c,0xcf,0xb5,0xb5,
+0xb7,0x06,0x0c,0x60,0xbc,0x4e,0x7d,0x77,0x13,0x07,0xf7,0x3f,0xf9,0x8f,0x05,0x67,
+0x13,0x07,0x07,0xc0,0x65,0x8f,0xd9,0x8f,0xbc,0xce,0x09,0xb5,0x79,0x54,0xfd,0xbb,
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_code_wlog.inc
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_code_wlog.inc
new file mode 100644
index 0000000000..8bef44974d
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_code_wlog.inc
@@ -0,0 +1,620 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x83,0x47,0x05,0x00,0x85,0x8b,0x99,0xc7,0x83,0xd7,0xc5,0xff,0x01,0x45,0x23,0x9f,
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+0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b,0x81,0xe7,0x13,0x05,0x30,0x10,0x82,0x80,
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+0x13,0x47,0x17,0x00,0x0e,0x07,0xb7,0x57,0xca,0x3f,0xb3,0xd5,0xe6,0x00,0x93,0x87,
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+0x06,0x01,0xb3,0x5e,0x67,0x02,0x13,0x98,0x06,0x01,0x13,0x58,0x08,0x01,0x33,0x16,
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+0x07,0x01,0x49,0x8f,0x76,0x85,0x63,0x7c,0xc7,0x01,0x36,0x97,0x13,0x85,0xfe,0xff,
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+0xc8,0x03,0x42,0x07,0xd9,0x8f,0x72,0x87,0x63,0xfc,0x07,0x01,0xb6,0x97,0x13,0x07,
+0xfe,0xff,0x63,0xe7,0xd7,0x00,0x63,0xf5,0x07,0x01,0x13,0x07,0xee,0xff,0xb6,0x97,
+0x42,0x05,0x41,0x6e,0x59,0x8d,0x93,0x06,0xfe,0xff,0x33,0x77,0xd5,0x00,0xb3,0x87,
+0x07,0x41,0xf1,0x8e,0x13,0x58,0x05,0x01,0x41,0x82,0x33,0x03,0xd7,0x02,0xb3,0x06,
+0xd8,0x02,0x33,0x07,0xc7,0x02,0x33,0x08,0xc8,0x02,0x33,0x06,0xd7,0x00,0x13,0x57,
+0x03,0x01,0x32,0x97,0x63,0x73,0xd7,0x00,0x72,0x98,0x93,0x56,0x07,0x01,0xc2,0x96,
+0x63,0xe0,0xd7,0x02,0xe3,0x97,0xd7,0xd8,0xc1,0x67,0xfd,0x17,0x7d,0x8f,0x42,0x07,
+0x33,0x73,0xf3,0x00,0xb3,0x98,0xb8,0x00,0x1a,0x97,0x81,0x45,0xe3,0xfc,0xe8,0xd6,
+0x7d,0x15,0x85,0xbb,0x81,0x45,0x01,0x45,0x82,0x80,
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_data.inc
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_data.inc
new file mode 100644
index 0000000000..a02f3b559f
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_data.inc
@@ -0,0 +1,22 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x72,0x03,0x38,0x40,0x56,0x05,0x38,0x40,0x00,0x00,0x38,0x40,0x68,0x07,0x38,0x40,
+0x7a,0x07,0x38,0x40,0x1a,0x00,0x38,0x40,0x36,0x06,0x38,0x40,0x32,0x00,0x38,0x40,
+0x44,0x00,0x38,0x40,0x00,0x00,0x00,0x00,0x5c,0x40,0xca,0x3f,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x68,0x00,0x38,0x40,
+0xde,0x00,0x38,0x40,0xae,0x00,0x38,0x40,0xe2,0x00,0x38,0x40,0x36,0x13,0x38,0x40,
+0x56,0x13,0x38,0x40,0x40,0x13,0x38,0x40,0x4a,0x13,0x38,0x40,0xcc,0x14,0x38,0x40,
+0x6e,0x13,0x38,0x40,0xca,0x13,0x38,0x40,0x36,0x14,0x38,0x40,0xcc,0x14,0x38,0x40,
+0x5c,0x13,0x38,0x40,0x62,0x13,0x38,0x40,0x96,0x14,0x38,0x40,0x00,0x00,0x04,0x00,
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x01,0x00,0x00,0x00,
+0x01,
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_data_wlog.inc
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_data_wlog.inc
new file mode 100644
index 0000000000..908df38118
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_data_wlog.inc
@@ -0,0 +1,289 @@
+/* Autogenerated with ../../../../../src/helper/bin2char.sh */
+0x1a,0x03,0x38,0x40,0xc4,0x06,0x38,0x40,0x00,0x00,0x38,0x40,0x08,0x09,0x38,0x40,
+0x1a,0x09,0x38,0x40,0x1a,0x00,0x38,0x40,0xa4,0x07,0x38,0x40,0x32,0x00,0x38,0x40,
+0x44,0x00,0x38,0x40,0x00,0x00,0x00,0x00,0x5c,0x40,0xca,0x3f,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+0xde,0x00,0x38,0x40,0xae,0x00,0x38,0x40,0xe2,0x00,0x38,0x40,0x53,0x54,0x55,0x42,
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+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+0x03,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_image.h
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_image.h
new file mode 100644
index 0000000000..0a8e8ffe6e
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_image.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define ESP32C2_STUB_BSS_SIZE 0x000013cUL
+
+#define ESP32C2_STUB_IRAM_ORG 0x040380000UL
+
+#define ESP32C2_STUB_IRAM_LEN 0x000004000UL
+
+#define ESP32C2_STUB_DRAM_ORG 0x03fca4000UL
+
+#define ESP32C2_STUB_DRAM_LEN 0x000020000UL
+
+#define ESP32C2_STUB_ENTRY_ADDR 0x04038115cUL
+
+#define ESP32C2_STUB_APPTRACE_CTRL_ADDR 0x03fca4144UL
+
+/*#define ESP32C2_STUB_BUILD_IDF_REV 2fdba8ec19
+*/
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_flasher_image_wlog.h
b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_image_wlog.h
new file mode 100644
index 0000000000..7f4cc01c21
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_flasher_image_wlog.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define ESP32C2_STUB_WLOG_BSS_SIZE 0x0001144UL
+
+#define ESP32C2_STUB_WLOG_LOG_ADDR 0x03fca5318UL
+
+#define ESP32C2_STUB_WLOG_LOG_SIZE 4100UL
+
+#define ESP32C2_STUB_WLOG_ENTRY_ADDR 0x040381aa6UL
+
+#define ESP32C2_STUB_WLOG_APPTRACE_CTRL_ADDR 0x03fca51f4UL
+
+/*#define ESP32C2_STUB_WLOG_BUILD_IDF_REV 2fdba8ec19
+*/
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_rom_chip.h
b/contrib/loaders/flash/espressif/esp32c2/stub_rom_chip.h
new file mode 100644
index 0000000000..86140a3003
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_rom_chip.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ * ESP32-C2 specific rom header files *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Erhan Kurubas <erhan.kuru...@espressif.com> *
+ ***************************************************************************/
+#ifndef ESP_STUB_ROM_H
+#define ESP_STUB_ROM_H
+
+#include "esp32c2/rom/ets_sys.h"
+#include "esp32c2/rom/spi_flash.h"
+#include "esp32c2/rom/spi_flash.h"
+#include "esp32c2/rom/cache.h"
+#include "esp32c2/rom/efuse.h"
+#include "esp32c2/rom/uart.h"
+#include "esp32c2/rom/rtc.h"
+#include "esp32c2/rom/sha.h"
+#include "miniz.h"
+
+#endif
diff --git a/contrib/loaders/flash/espressif/esp32c2/stub_sha.c
b/contrib/loaders/flash/espressif/esp32c2/stub_sha.c
new file mode 100644
index 0000000000..4dda8077cf
--- /dev/null
+++ b/contrib/loaders/flash/espressif/esp32c2/stub_sha.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD */
+
+#include <string.h>
+#include "stub_rom_chip.h"
+
+static SHA_CTX ctx;
+
+/* this function has the same implementation for ESP32-S2
+ * TODO: move to common file */
+void stub_sha256_start(void)
+{
+ /* Enable SHA hardware */
+ ets_sha_enable();
+ ets_sha_init(&ctx, SHA2_256);
+}
+
+void stub_sha256_data(const void *data, size_t data_len)
+{
+ /* C2 secure boot key field consists of 1 byte of curve identifier and
64 bytes of ECDSA public key.
+ * While verifying the signature block, we need to calculate the SHA of
this key field which is of 65 bytes.
+ * ets_sha_update handles it cleanly so we can safely remove the check:
+ * assert(data_len % 4) == 0
+ */
+ ets_sha_update(&ctx, data, data_len, false);
+}
+
+void stub_sha256_finish(uint8_t *digest)
+{
+ if (!digest) {
+ bzero(&ctx, sizeof(ctx));
+ return;
+ }
+ ets_sha_finish(&ctx, digest);
+ ets_sha_disable();
+}
--
