[PATCH]: 9d9c9db4eb target/xtensa: extra debug info for "xtensa exe" failures

[gerrit]

This is an automated email from Gerrit.

"Ian Thompson <ia...@cadence.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/7982

-- gerrit

commit 9d9c9db4eb348724b800dbab29c0ea8c1df8fa5d
Author: ianst <ia...@cadence.com>
Date:   Wed Dec 6 14:34:09 2023 -0800

    target/xtensa: extra debug info for "xtensa exe" failures
    
    - Read and display EXCCAUSE on exe error
    - Clean up error messages
    - Clarify "xtensa exe" documentation
    
    Signed-off-by: ianst <ia...@cadence.com>
    Change-Id: I90ed39f6afb6543c0c873301501435384b4dccbe

diff --git a/doc/openocd.texi b/doc/openocd.texi
index db7315fe44..9c9be0d63d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11496,8 +11496,9 @@ This feature is not well implemented and tested yet.
 @end deffn
 
 @deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
-Execute arbitrary instruction(s) provided as an ascii string.  The string 
represents an integer
-number of instruction bytes, thus its length must be even.
+Execute one arbitrary instruction provided as an ascii string.  The string 
represents an integer
+number of instruction bytes, thus its length must be even.  The instruction 
can be of any width
+that is valid for the Xtensa core configuration.
 @end deffn
 
 @deffn {Command} {xtensa dm} (address) [value]
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 85dce0614c..30c7ee0a8e 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -3274,15 +3274,21 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target 
*target)
        LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]);
        xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap 
*/
        status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
-       if (status != ERROR_OK)
-               LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status);
-       status = xtensa_core_status_check(target);
-       if (status != ERROR_OK)
-               LOG_TARGET_ERROR(target, "TIE instr execute: %d\n", status);
+       if (status != ERROR_OK) {
+               LOG_TARGET_ERROR(target, "exec: queue error %" PRId32, status);
+       } else {
+               status = xtensa_core_status_check(target);
+               if (status != ERROR_OK)
+                       LOG_TARGET_ERROR(target, "exec: status error %" PRId32, 
status);
+       }
 
        /* Reread register cache and restore saved regs after instruction 
execution */
        if (xtensa_fetch_all_regs(target) != ERROR_OK)
-               LOG_TARGET_ERROR(target, "%s: Failed to fetch register cache 
(post-exec).", target_name(target));
+               LOG_TARGET_ERROR(target, "post-exec: register fetch error");
+       if (status != ERROR_OK) {
+               LOG_TARGET_ERROR(target, "post-exec: EXCCAUSE 0x%02" PRIx32,
+                       xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE));
+       }
        xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause);
        xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable);
        return status;

--