This is an automated email from Gerrit.
"Antonio Borneo <borneo.anto...@gmail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8129
-- gerrit
commit de9e12bc3df696b236161c319ebf82b81d2e1b80
Author: Antonio Borneo <borneo.anto...@gmail.com>
Date: Sat Feb 3 19:25:21 2024 +0100
doc: document 'target create' flags '-dbgbase' and '-coreid'
Add to the command 'target create' the description for the flags
'-dbgbase' and '-coreid'.
Report that '-coreid' is currently used for purposes other than
CPU detection/examination, and that such uses are going to be
re-considered.
Change-Id: I25c839e3653101234c5862ce9da77019a5bb3249
Signed-off-by: Antonio Borneo <borneo.anto...@gmail.com>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index e4d4dc5d68..6ba93379e1 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5153,6 +5153,25 @@ On ADIv6 DAP @var{ap_number} is the base address of the
DAP AP the target is con
Use this option with systems where multiple, independent cores are connected
to separate access ports of the same DAP.
+@item @code{-dbgbase} @var{dbg_base_address} -- set the base address of the
+debug controller.
+This is ignored and not required for target types that use fixed addresses,
+like @code{cortex_m}.
+OpenOCD can parse the ROM table in the DAP access port to identify this
+base address, but the parsing can be slow on devices with big ROM tables.
+Either to speed up the target examination and to address devices with
+incorrect ROM table content, it's suggested to use @code{-dbgbase}.
+
+@item @code{-coreid} @var{coreid} -- set the position of target in DAP access
port
+For devices with multiple CPUs on the same DAP access port (e.g.
@code{cortex_a},
+@code{cortex_r4}, @code{aarch64} and @code{armv8r}), specify that the ROM table
+parsing should select the CPU in position @var{coreid}.
+When @code{-dbgbase} option is provide, this option is not used to identify
+the CPU.
+This value @var{coreid} is currently also used in other contexts as a general
+CPU index, e.g. in SMP nodes or to select a specific CPU in a chip.
+To avoid confusion, these additional use cases are going to be dropped.
+
@item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
to the target. Currently, only the @code{aarch64} target makes use of this
option,
where it is a mandatory configuration for the target run control.
--
