[PATCH]: 55ec6f0205 target/risc-v: add RTT commands

[gerrit]

This is an automated email from Gerrit.

"Evgeniy Morozov <morozov.evgeniy...@gmail.com>" just uploaded a new patch set 
to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8234

-- gerrit

commit 55ec6f02058a3d1538557c023aab76332ac4740c
Author: Morozov-5F <morozov.evgeniy...@gmail.com>
Date:   Mon May 6 20:07:23 2024 +0300

    target/risc-v: add RTT commands
    
    The original patch to add the SEGGER RTT tooling added it only for ARM
    devices. But now JLink supports RISC-V targets and we can now add the
    RTT command domain to the RISC-V target. I've tested this on my RISC-V
    32-bit chip and it appears to be working - I was able to communicate with
    the device using the RTT.
    
    Change-Id: I6adc79b92d3ef80c641ffe4675fdd2b8389ae306
    Signed-off-by: Morozov-5F <morozov.evgeniy...@gmail.com>

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 9cd4922d20..ebddda0a42 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -22,6 +22,7 @@
 #include "rtos/rtos.h"
 #include "debug_defines.h"
 #include <helper/bits.h>
+#include <rtt/rtt.h>
 
 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & 
~((mask) << 1))) & (mask)))
@@ -3049,6 +3050,9 @@ static const struct command_registration 
riscv_command_handlers[] = {
                .usage = "",
                .chain = semihosting_common_handlers
        },
+       {
+               .chain = rtt_target_command_handlers,
+       },
        COMMAND_REGISTRATION_DONE
 };
 

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