This is an automated email from Gerrit.
"Bernhard Rosenkränzer <b...@baylibre.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8295
-- gerrit
commit 85c2b3aab9946e9bc0d2667dfd22089ef1024a12
Author: Anatoly Parshintsev <114445139+aap...@users.noreply.github.com>
Date: Wed Feb 15 20:53:37 2023 +0300
target/riscv: hide_csrs configuration option
This option allows users to mark certain CSRs as hidden so they could be
expluded from *reg* output and target.xml
This is based on the work by Anatoly Parshintsev
<114445139+aap...@users.noreply.github.com>
and Jan Matyas <50193733+janmatcoda...@users.noreply.github.com> in the
RISC-V fork of OpenOCD.
Change-Id: I8b4a166c933e7de752b193a855afe24ac51356de
Signed-off-by: Bernhard Rosenkränzer <b...@baylibre.com>
Signed-off-by: Anatoly Parshintsev
<114445139+aap...@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+janmatcoda...@users.noreply.github.com>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 55e6e76808..ad79c98399 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11207,10 +11207,28 @@ $_TARGETNAME expose_custom 32=myregister
@end example
@end deffn
+<<<<<<< HEAD
@deffn {Command} {riscv info}
Displays some information OpenOCD detected about the target.
@end deffn
+@deffn {Config Command} {riscv hide_csrs} n[-m] [,n1[-m1]] [...]
+The RISC-V Specification defines many CSRs, and we may want to avoid showing
+each CSR to the user, as they may not be relevant to the task at hand. For
+example, we may choose not to show trigger or PMU registers for simple
+debugging scenarios. This command allows to mark individual registers or
+register ranges (inclusive) as "hidden". Such hidden registers won't be
+displayed in GDB or @code{reg} command output.
+
+@example
+
+# Hide range of RISC-V CSRs
+# CSR_TSELECT - 1952 and CSR_TDATA1 - 1953
+$_TARGETNAME riscv hide_csrs 1952-1953
+
+@end example
+@end deffn
+
@deffn {Command} {riscv reset_delays} [wait]
OpenOCD learns how many Run-Test/Idle cycles are required between scans to
avoid
encountering the target being busy. This command resets those learned values
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 9cd4922d20..b5bdeaafcf 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -502,6 +502,11 @@ static void riscv_deinit_target(struct target *target)
return;
range_list_t *entry, *tmp;
+ list_for_each_entry_safe(entry, tmp, &info->hide_csr, list) {
+ free(entry->name);
+ free(entry);
+ }
+
list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
free(entry->name);
free(entry);
@@ -2592,6 +2597,26 @@ COMMAND_HANDLER(riscv_set_expose_custom)
return ret;
}
+COMMAND_HANDLER(riscv_hide_csrs)
+{
+ if (CMD_ARGC == 0) {
+ LOG_ERROR("Command expects parameters");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ struct target *target = get_current_target(CMD_CTX);
+ RISCV_INFO(info);
+ int ret = ERROR_OK;
+
+ for (unsigned int i = 0; i < CMD_ARGC; i++) {
+ ret = parse_ranges(&info->hide_csr, CMD_ARGV[i], "csr", 0xfff);
+ if (ret != ERROR_OK)
+ break;
+ }
+
+ return ret;
+}
+
COMMAND_HANDLER(riscv_authdata_read)
{
unsigned int index = 0;
@@ -2918,6 +2943,16 @@ static const struct command_registration
riscv_exec_command_handlers[] = {
"expose. custom0 is accessed as abstract register
number 0xc000, "
"etc. This must be executed before `init`."
},
+ {
+ .name = "hide_csrs",
+ .handler = riscv_hide_csrs,
+ .mode = COMMAND_CONFIG,
+ .usage = "{n0|n-m0}[,n1|n-m1]......",
+ .help = "Configure a list of inclusive ranges for CSRs to hide
from gdb. "
+ "Hidden registers are still available, but are not
listed in "
+ "gdb target description and `reg` command output. "
+ "This must be executed before `init`."
+ },
{
.name = "authdata_read",
.handler = riscv_authdata_read,
@@ -3141,6 +3176,7 @@ static void riscv_info_init(struct target *target, struct
riscv_info *r)
INIT_LIST_HEAD(&r->expose_csr);
INIT_LIST_HEAD(&r->expose_custom);
+ INIT_LIST_HEAD(&r->hide_csr);
}
static int riscv_resume_go_all_harts(struct target *target)
@@ -4350,6 +4386,14 @@ int riscv_init_registers(struct target *target)
r->exist = true;
break;
}
+ } else if (r->exist && !list_empty(&info->hide_csr)) {
+ range_list_t *entry;
+ list_for_each_entry(entry, &info->hide_csr,
list)
+ if ((entry->low <= csr_number) &&
(csr_number <= entry->high)) {
+ LOG_TARGET_DEBUG(target,
"Hiding CSR %d (name=%s)", csr_number, r->name);
+ r->hidden = true;
+ break;
+ }
}
} else if (number == GDB_REGNO_PRIV) {
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index aba0864e6d..304f0ed8e6 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -224,6 +224,10 @@ struct riscv_info {
* from range 0xc000 ... 0xffff. */
struct list_head expose_custom;
+ /* The list of registers to mark as "hidden". Hidden registers are
available
+ * but do not appear in gdb targets description or reg command output.
*/
+ struct list_head hide_csr;
+
riscv_sample_config_t sample_config;
struct riscv_sample_buf sample_buf;
};
--
