This is an automated email from Gerrit.
"Marek Kraus <gamelas...@outlook.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/8529
-- gerrit
commit 253e28e3d965691a9c86025596ec3d34133b8378
Author: Marek Kraus <gamelas...@outlook.com>
Date: Wed Oct 23 16:27:33 2024 +0200
tcl/target/bl702: implement full software reset
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelas...@outlook.com>
diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg
index 6d4a048d90..e23253a04e 100644
--- a/tcl/target/bl702.cfg
+++ b/tcl/target/bl702.cfg
@@ -34,27 +34,48 @@ $_TARGETNAME configure -work-area-phys 0x22020000
-work-area-size 0x10000 -work-
# Internal RC ticks on 32 MHz, so this speed should be safe to use.
adapter speed 4000
-$_TARGETNAME configure -event reset-assert-pre {
+# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do
SW reset instead.
+# CTRL_PWRON_RESET triggers full "power-on like" reset.
+# This means that pinmux configuration to access JTAG is reset as well, and
configured back early
+# in BootROM. Since we will lose JTAG access, and RISC-V Debug Module is (most
likely) reset too,
+# we can override default assert_reset C function behavior, perform full SW
reset
+# and let OpenOCD re-attach again.
+$_TARGETNAME configure -event reset-assert {
halt
# Switch clock to internal RC32M
- # In HBN_GLB, set ROOT_CLK_SEL = 0
- mmw 0x4000f030 0x0 0x00000003
- # Wait for clock switch
- sleep 10
-
- # GLB_REG_BCLK_DIS_FALSE
- mww 0x40000ffc 0x0
-
- # HCLK is RC32M, so BCLK/HCLK doesn't need divider
- # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
- mmw 0x40000000 0x0 0x00FFFF00
- # Wait for clock to stabilize
- sleep 10
-
- # Do reset
- # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET
- mmw 0x40000018 0x0 0x00000007
- # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET to 1
- mmw 0x40000018 0x6 0x0
+ # In HBN_GLB, set ROOT_CLK_SEL = 0
+ mmw 0x4000f030 0x0 0x00000003
+ # Wait for clock switch
+ sleep 10
+
+ # GLB_REG_BCLK_DIS_FALSE
+ mww 0x40000ffc 0x0
+
+ # HCLK is RC32M, so BCLK/HCLK doesn't need divider
+ # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+ mmw 0x40000000 0x0 0x00FFFF00
+ # Wait for clock to stabilize
+ sleep 10
+
+ # We need to trigger the final sw reset by few instructions, because
both
+ # progbuf and sysbus mem access complains about that it cannot get
+ # status if the write was successful or not, since chip is already
reset.
+ # Since this chip does not support abstract access, this is the only
option.
+
+ ## In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET
+ # lw t1, 0(a1) # Load the value from the address in a1
(GLB_SWRST_CFG2) into t1
+ # li t2, 0xFFFFFFF8 # Load the mask value of 0x7 (bitfields) into
t2
+ # and t1, t1, t2 # AND t1 with t2 and store result back in t1
+ # sw t1, 0(a1) # Store the cleared reg value to the address
in a1 (GLB_SWRST_CFG2)
+ ## In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and
CTRL_PWRON_RESET to 1
+ # li t1, 0x7 # Load the value 0x7 (bitfields) into t1
+ # sw t1, 0(a1) # Store the value 0x7 to the address in a1
(GLB_SWRST_CFG2)
+ reg a1 0x40000018
+ reg pc 0x22014000
+ # We put those instructions into DTCM, in case ITCM is already used by
L1C
+ write_memory 0x22014000 32 { 0x0005a303 0xff800393 0x00737333
0x0065a023 0x00700313 0x0065a023 }
+
+ # Let CPU to execute it and trigger full sw reset
+ resume
}
--
