Hi Ross, > I’m working on an industrial production test device that needs to be > able to interact with parts under test via JTAG/SWD to: > * Write to RAM > * Write to the flash > * Start execution at specific addresses > * Provide single step environment for the device under test (during > development mode) > * Support arm (cortex and later) and riscv targets > > We’re developing this testing platform with a Zynq Ultrascale as the > CPU running a scripting language and I hope/plan on using OpenOCD as > my tool to interact with the parts during testing.
Sounds reasonable and a perfect use case for OpenOCD. > To reduce test time, we plan on putting a JTAG/SWD hardware block > into the programmable logic that will reliably and quickly clock bits > in and out. It’s unclear to me what the peripheral interface to > userland needs to be and I was trying to find the layer in OpenOCD > that best fits what I’m trying to do. > > I assume it’s something like: > * Write bitstream > * Read bitstream > * Write bits, then read bits (or the opposite, or both) > * Force interface bits (TMS, TDO, TCLK, etc.) in a particular > direction for a set time (or number of clocks) > * Set clock speed > > But I can’t quite find that interface. Looking through the > jtag/drivers directory, I’ve found… Most of the drivers have a lot of JTAG / SWD (queuing) logic inside but in the end it boils down to a few functions that write and read a number of bits to/from the adapter. In case of the XLNX-PCIE-XVC driver this is xlnx_pcie_xvc_transact(). For the J-Link driver it is jlink_flush(), which makes a call to libjaylink to transfer the TMS, TDI and TDO data over USB to the J-Link adapter. For your driver you just need to use one of these drivers as basis and implement your hardware/FPGA adapter hardware API. This could be, for example, some shared memory nd between userland and your "adapter" on the FPGA. I hope I was able to help you a little further, if you have any questions please feel free to ask. Best regards Marc
