This is an automated email from Gerrit.
"Ryan QIAN <jianghao.q...@outlook.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8697
-- gerrit
commit 9f247d8b4254699315b335a2b06e0c1bf71913ae
Author: Ryan QIAN <jianghao.q...@hpmicro.com>
Date: Tue Jan 7 15:21:02 2025 +0800
tcl: add config file for hpmicro devices and boards
- add board and device config files
Change-Id: I8afb0b734b1064d71c4af3c118c7777d0ead9e6b
Signed-off-by: Ryan QIAN <jianghao.q...@hpmicro.com>
diff --git a/tcl/board/hpm5300evk.cfg b/tcl/board/hpm5300evk.cfg
new file mode 100644
index 0000000000..7d495f5b38
--- /dev/null
+++ b/tcl/board/hpm5300evk.cfg
@@ -0,0 +1,79 @@
+# Copyright (c) 2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit
address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit 6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed
by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should
be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 -
120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected
to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3000000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6
0x1000
+
+proc init_clock {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
+
+$_TARGET0 configure -event gdb-attach {
+ reset halt
+}
diff --git a/tcl/board/hpm6200evk.cfg b/tcl/board/hpm6200evk.cfg
new file mode 100644
index 0000000000..ed5b5ce345
--- /dev/null
+++ b/tcl/board/hpm6200evk.cfg
@@ -0,0 +1,33 @@
+# Copyright (c) 2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
+
+proc init_clock {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
+
+$_TARGET0 configure -event gdb-attach {
+ reset halt
+}
diff --git a/tcl/board/hpm6300evk.cfg b/tcl/board/hpm6300evk.cfg
new file mode 100644
index 0000000000..ca3c8db664
--- /dev/null
+++ b/tcl/board/hpm6300evk.cfg
@@ -0,0 +1,236 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
+
+proc init_clock {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure femc frequency
+# 166Mhz pll0_clk1: 333Mhz divide by 2
+ $::_TARGET0 riscv dmi_write 0x39 0xF4001808
+ $::_TARGET0 riscv dmi_write 0x3C 0x201
+
+ # PA25
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400C8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PA26
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400D0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PA27
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400D8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PA28
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400E0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PA29
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400E8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PA30
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400F0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PA31
+ $::_TARGET0 riscv dmi_write 0x39 0xF40400F8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB00
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040100
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB01
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040108
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB02
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040110
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB03
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040118
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB04
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040120
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB05
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040128
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB06
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040130
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB07
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040138
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB08
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040140
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # PB09
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040148
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB10
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040150
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB11
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040158
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB12
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040160
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB13
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040168
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB14
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040170
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB15
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040178
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB16
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040180
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB17
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040188
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB18
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040190
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB19
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040198
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB20
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401A0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # PB21
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401A8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB22
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401B0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB23
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401B8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB24
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401C0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB25
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401C8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB26
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401D0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB27
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401D8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB28
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401E0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB29
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401E8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB30
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401F0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB31
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401F8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # femc configuration
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+ sleep 10
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050008
+ $::_TARGET0 riscv dmi_write 0x3C 0x30524
+ $::_TARGET0 riscv dmi_write 0x39 0xF305000C
+ $::_TARGET0 riscv dmi_write 0x3C 0x6030524
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+ $::_TARGET0 riscv dmi_write 0x3C 0x10000004
+
+ # 32MB
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050010
+ $::_TARGET0 riscv dmi_write 0x3C 0x4000001b
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050014
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ # 16-bit
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050040
+ $::_TARGET0 riscv dmi_write 0x3C 0xf31
+
+ # 166Mhz configuration
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050044
+ $::_TARGET0 riscv dmi_write 0x3C 0x884e33
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+ $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+ $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+ $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+ $::_TARGET0 riscv dmi_write 0x3C 0x2020300
+
+ # config delay cell
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+ $::_TARGET0 riscv dmi_write 0x3C 0x2000
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050094
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050098
+ $::_TARGET0 riscv dmi_write 0x3C 0
+
+ # precharge all
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050090
+ $::_TARGET0 riscv dmi_write 0x3C 0x40000000
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+ # auto refresh
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+ # set mode
+ $::_TARGET0 riscv dmi_write 0x39 0xF30500A0
+ $::_TARGET0 riscv dmi_write 0x3C 0x33
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+ $::_TARGET0 riscv dmi_write 0x3C 0x2020301
+ echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_sdram
+}
+
+$_TARGET0 configure -event gdb-attach {
+ reset halt
+}
diff --git a/tcl/board/hpm6750evk.cfg b/tcl/board/hpm6750evk.cfg
new file mode 100644
index 0000000000..2953e08f86
--- /dev/null
+++ b/tcl/board/hpm6750evk.cfg
@@ -0,0 +1,345 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit
address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit 6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed
by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should
be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 -
120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected
to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3040000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7
+
+proc init_clock {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure femc frequency
+# 133Mhz pll1_clk0: 266Mhz divide by 2
+ #$::_TARGET0 riscv dmi_write 0x39 0xF4001820
+ #$::_TARGET0 riscv dmi_write 0x3C 0x201
+# 166Mhz pll2_clk0: 333Mhz divide by 2
+ $::_TARGET0 riscv dmi_write 0x39 0xF4001820
+ $::_TARGET0 riscv dmi_write 0x3C 0x401
+ # PC01
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040208
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC00
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040200
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB31
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401F8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB30
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401F0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB29
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401E8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB28
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401E0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB27
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401D8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB26
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401D0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB25
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401C8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB24
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401C0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB23
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401B8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB22
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401B0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB21
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401A8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB20
+ $::_TARGET0 riscv dmi_write 0x39 0xF40401A0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB19
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040198
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PB18
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040190
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # PD13
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040368
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD12
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040360
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD10
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040350
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD09
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040348
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD08
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040340
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD07
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040338
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD06
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040330
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD05
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040328
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD04
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040320
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD03
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040318
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD02
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040310
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD01
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040308
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PD00
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040300
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC29
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402E8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC28
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402E0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC27
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402D8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # PC22
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402B0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC21
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402A8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC17
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040288
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC15
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040278
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC12
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040260
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC11
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040258
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC10
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040250
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC09
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040248
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC08
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040240
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC07
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040238
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC06
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040230
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC05
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040228
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC04
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040220
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # PC14
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040270
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC13
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040268
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC16
+ # $::_TARGET0 riscv dmi_write 0x39 0xF4040280
+ $::_TARGET0 riscv dmi_write 0x3C 0x1000C
+ # PC26
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402D0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC25
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402C8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC19
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040298
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC18
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040290
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC23
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402B8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC24
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402C0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC30
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402F0
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC31
+ $::_TARGET0 riscv dmi_write 0x39 0xF40402F8
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC02
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040210
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+ # PC03
+ $::_TARGET0 riscv dmi_write 0x39 0xF4040218
+ $::_TARGET0 riscv dmi_write 0x3C 0xC
+
+ # femc configuration
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+ sleep 10
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050008
+ $::_TARGET0 riscv dmi_write 0x3C 0x30524
+ $::_TARGET0 riscv dmi_write 0x39 0xF305000C
+ $::_TARGET0 riscv dmi_write 0x3C 0x6030524
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050000
+ $::_TARGET0 riscv dmi_write 0x3C 0x10000000
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050010
+ $::_TARGET0 riscv dmi_write 0x3C 0x4000001b
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050014
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050040
+ $::_TARGET0 riscv dmi_write 0x3C 0xf32
+
+ # 133Mhz configuration
+ #$::_TARGET0 riscv dmi_write 0x39 0xF3050044
+ #$::_TARGET0 riscv dmi_write 0x3C 0x884e22
+ # 166Mhz configuration
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050044
+ $::_TARGET0 riscv dmi_write 0x3C 0x884e33
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+ $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050048
+ $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d
+ $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+ $::_TARGET0 riscv dmi_write 0x3C 0x2020300
+
+ # config delay cell
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+ $::_TARGET0 riscv dmi_write 0x3C 0x3b
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050150
+ $::_TARGET0 riscv dmi_write 0x3C 0x203b
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050094
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050098
+ $::_TARGET0 riscv dmi_write 0x3C 0
+
+ # precharge all
+ $::_TARGET0 riscv dmi_write 0x39 0xF3050090
+ $::_TARGET0 riscv dmi_write 0x3C 0x40000000
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+ # auto refresh
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+ # set mode
+ $::_TARGET0 riscv dmi_write 0x39 0xF30500A0
+ $::_TARGET0 riscv dmi_write 0x3C 0x33
+ $::_TARGET0 riscv dmi_write 0x39 0xF305009C
+ $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A
+ sleep 500
+ $::_TARGET0 riscv dmi_write 0x39 0xF305003C
+ $::_TARGET0 riscv dmi_write 0x3C 0x3
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF305004C
+ $::_TARGET0 riscv dmi_write 0x3C 0x2020301
+ echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_sdram
+}
+
+$_TARGET0 configure -event gdb-attach {
+ reset halt
+}
diff --git a/tcl/board/hpm6800evk.cfg b/tcl/board/hpm6800evk.cfg
new file mode 100644
index 0000000000..e5f25c0ee1
--- /dev/null
+++ b/tcl/board/hpm6800evk.cfg
@@ -0,0 +1,215 @@
+# Copyright (c) 2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
+
+proc init_clock {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_ddr3 {} {
+# ddr dcdc setup
+ $::_TARGET0 riscv dmi_write 0x39 0xF4104080
+ $::_TARGET0 riscv dmi_write 0x3C 0x10578
+
+# ddr3 setup
+ $::_TARGET0 riscv dmi_write 0x39 0xF40C0180
+ $::_TARGET0 riscv dmi_write 0x3C 0x30000019
+ $::_TARGET0 riscv dmi_write 0x39 0xF400180C
+ $::_TARGET0 riscv dmi_write 0x3C 0x09100401
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4153000
+ $::_TARGET0 riscv dmi_write 0x3C 0xF0000010
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF30101B0
+ $::_TARGET0 riscv dmi_write 0x3C 0
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150040
+ $::_TARGET0 riscv dmi_write 0x3C 0xf004641f
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4153000
+ $::_TARGET0 riscv dmi_write 0x3C 0xf0000011
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3013000
+ $::_TARGET0 riscv dmi_write 0x3C 0xf4000000
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010490
+ $::_TARGET0 riscv dmi_write 0x3C 1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1040001
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF30100D0
+ $::_TARGET0 riscv dmi_write 0x3C 0x4002004e
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010110
+ $::_TARGET0 riscv dmi_write 0x3C 0x05010407
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010190
+ $::_TARGET0 riscv dmi_write 0x3C 0x07040102
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010194
+ $::_TARGET0 riscv dmi_write 0x3C 0x20404
+ $::_TARGET0 riscv dmi_write 0x39 0xF30101A4
+ $::_TARGET0 riscv dmi_write 0x3C 0x20008
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010240
+ $::_TARGET0 riscv dmi_write 0x3C 0x06000600
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010200
+ $::_TARGET0 riscv dmi_write 0x3C 0x1F1F1F
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010204
+ $::_TARGET0 riscv dmi_write 0x3C 0x121212
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010208
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF301020C
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010210
+ $::_TARGET0 riscv dmi_write 0x3C 0x1F1F
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010214
+ $::_TARGET0 riscv dmi_write 0x3C 0x06030303
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010218
+ $::_TARGET0 riscv dmi_write 0x3C 0x0F060606
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3013000
+ $::_TARGET0 riscv dmi_write 0x3C 0xFC000000
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150054
+ $::_TARGET0 riscv dmi_write 0x3C 0xc70
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150058
+ $::_TARGET0 riscv dmi_write 0x3C 0x6
+ $::_TARGET0 riscv dmi_write 0x39 0xF415005c
+ $::_TARGET0 riscv dmi_write 0x3C 0x18
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150048
+ $::_TARGET0 riscv dmi_write 0x3C 0x919c8866
+ $::_TARGET0 riscv dmi_write 0x39 0xF415004c
+ $::_TARGET0 riscv dmi_write 0x3C 0x1a838360
+ $::_TARGET0 riscv dmi_write 0x39 0xF415008c
+ $::_TARGET0 riscv dmi_write 0x3C 0xf06d50
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150050
+ $::_TARGET0 riscv dmi_write 0x3C 0x3002d200
+
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF30101b0
+ $::_TARGET0 riscv dmi_write 0x3C 1
+ sleep 100
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150068
+ $::_TARGET0 riscv dmi_write 0x3C 0x930035C7
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150004
+ $::_TARGET0 riscv dmi_write 0x3C 0xFF81
+ sleep 200
+
+ echo "ddr3 has been enabled!"
+}
+
+proc init_dram {} {
+# ddr dcdc setup
+ $::_TARGET0 riscv dmi_write 0x39 0xF4104080
+ $::_TARGET0 riscv dmi_write 0x3C 0x10708
+
+# pll1 setup
+ $::_TARGET0 riscv dmi_write 0x39 0xF40c0180
+ $::_TARGET0 riscv dmi_write 0x3C 0xb0000016
+ $::_TARGET0 riscv dmi_write 0x39 0xF40c0184
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF40c0188
+ $::_TARGET0 riscv dmi_write 0x3C 0xe4e1c00
+
+#ddr setup
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010000
+ $::_TARGET0 riscv dmi_write 0x3C 0x3040000
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF30101B0
+ $::_TARGET0 riscv dmi_write 0x3C 0
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150044
+ $::_TARGET0 riscv dmi_write 0x3C 0x40a
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150040
+ $::_TARGET0 riscv dmi_write 0x3C 0xf004641f
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4153000
+ $::_TARGET0 riscv dmi_write 0x3C 0xf0000011
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3013000
+ $::_TARGET0 riscv dmi_write 0x3C 0xf4000000
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010490
+ $::_TARGET0 riscv dmi_write 0x3C 1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1040000
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010190
+ $::_TARGET0 riscv dmi_write 0x3C 0x07010101
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010194
+ $::_TARGET0 riscv dmi_write 0x3C 0x20404
+ $::_TARGET0 riscv dmi_write 0x39 0xF30101A4
+ $::_TARGET0 riscv dmi_write 0x3C 0x20008
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010240
+ $::_TARGET0 riscv dmi_write 0x3C 0x6000600
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010200
+ $::_TARGET0 riscv dmi_write 0x3C 0x1f1f1f
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010204
+ $::_TARGET0 riscv dmi_write 0x3C 0x70707
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010208
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF301020c
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010210
+ $::_TARGET0 riscv dmi_write 0x3C 0x1f1f
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010214
+ $::_TARGET0 riscv dmi_write 0x3C 0x6060606
+ $::_TARGET0 riscv dmi_write 0x39 0xF3010218
+ $::_TARGET0 riscv dmi_write 0x3C 0xf0f0606
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF3013000
+ $::_TARGET0 riscv dmi_write 0x3C 0xfc000000
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150020
+ $::_TARGET0 riscv dmi_write 0x3C 0x3000100
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150028
+ $::_TARGET0 riscv dmi_write 0x3C 0x18002356
+ $::_TARGET0 riscv dmi_write 0x39 0xF415002c
+ $::_TARGET0 riscv dmi_write 0x3C 0x0aac4156
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150054
+ $::_TARGET0 riscv dmi_write 0x3C 0xe73
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150058
+ $::_TARGET0 riscv dmi_write 0x3C 0x5
+ $::_TARGET0 riscv dmi_write 0x39 0xF415005c
+ $::_TARGET0 riscv dmi_write 0x3C 0
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150048
+ $::_TARGET0 riscv dmi_write 0x3C 0xf2adfe53
+ $::_TARGET0 riscv dmi_write 0x39 0xF415004c
+ $::_TARGET0 riscv dmi_write 0x3C 0x22820362
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150050
+ $::_TARGET0 riscv dmi_write 0x3C 0x30020100
+ $::_TARGET0 riscv dmi_write 0x39 0xF415008c
+ $::_TARGET0 riscv dmi_write 0x3C 0xf06d50
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF30101b0
+ $::_TARGET0 riscv dmi_write 0x3C 1
+ sleep 100
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150068
+ $::_TARGET0 riscv dmi_write 0x3C 0x91003587
+ $::_TARGET0 riscv dmi_write 0x39 0xF4150004
+ $::_TARGET0 riscv dmi_write 0x3C 0xF501
+ sleep 200
+ echo "ddr has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_ddr3
+}
+
+$_TARGET0 configure -event gdb-attach {
+ reset halt
+}
diff --git a/tcl/board/hpm6e00evk.cfg b/tcl/board/hpm6e00evk.cfg
new file mode 100644
index 0000000000..3147f1b559
--- /dev/null
+++ b/tcl/board/hpm6e00evk.cfg
@@ -0,0 +1,80 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit
address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit 6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed
by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should
be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 -
120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected
to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3000000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
+
+proc init_clock {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+ $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+ $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
+
+$_TARGET0 configure -event gdb-attach {
+ reset halt
+}
diff --git a/tcl/target/hpmicro/hpm5300.cfg b/tcl/target/hpmicro/hpm5300.cfg
new file mode 100644
index 0000000000..454d6893ae
--- /dev/null
+++ b/tcl/target/hpmicro/hpm5300.cfg
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm5361
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr_lite.cfg]
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF410001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6280-dual-core.cfg
b/tcl/target/hpmicro/hpm6280-dual-core.cfg
new file mode 100644
index 0000000000..e0dd188348
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6280-dual-core.cfg
@@ -0,0 +1,62 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+set _CHIP hpm6280
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc dmi_write {reg value} {
+ $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc dmi_read {reg} {
+ set v [$::_TARGET0 riscv dmi_read ${reg}]
+ return ${v}
+}
+proc dmi_write_memory {addr value} {
+ dmi_write 0x39 ${addr}
+ dmi_write 0x3C ${value}
+}
+
+proc dmi_read_memory {addr} {
+ set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
+ dmi_write 0x38 ${sbcs}
+ dmi_write 0x39 ${addr}
+ set value [dmi_read 0x3C]
+ return ${value}
+}
+
+proc release_core1 {} {
+ dmi_write_memory 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+$_TARGET1 configure -event examine-start {
+ release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+ $::_TARGET0 arp_poll
+ release_core1
+}
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF40C001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6280-single-core.cfg
b/tcl/target/hpmicro/hpm6280-single-core.cfg
new file mode 100644
index 0000000000..198db24391
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6280-single-core.cfg
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6280
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF40C001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6360.cfg b/tcl/target/hpmicro/hpm6360.cfg
new file mode 100644
index 0000000000..ea23235856
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6360.cfg
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6360
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF40C001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6750-dual-core.cfg
b/tcl/target/hpmicro/hpm6750-dual-core.cfg
new file mode 100644
index 0000000000..4bd8cc52ca
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6750-dual-core.cfg
@@ -0,0 +1,76 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+set _CHIP hpm6750
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc dmi_write {reg value} {
+ $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc dmi_read {reg} {
+ set v [$::_TARGET0 riscv dmi_read ${reg}]
+ return ${v}
+}
+proc dmi_write_memory {addr value} {
+ dmi_write 0x39 ${addr}
+ dmi_write 0x3C ${value}
+}
+
+proc dmi_read_memory {addr} {
+ set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
+ dmi_write 0x38 ${sbcs}
+ dmi_write 0x39 ${addr}
+ set value [dmi_read 0x3C]
+ return ${value}
+}
+
+proc release_core1 {} {
+
+ set chip_rev [dmi_read_memory 0x2001FF00]
+
+ if {$chip_rev != 0x56010100 } {
+ # set start point for core1
+ dmi_write_memory 0xF4002C08 0x20016284
+ } else {
+ dmi_write_memory 0xF4002C08 0x2001660c
+ }
+
+ # set boot flag for core1
+ dmi_write_memory 0xF4002C0C 0xC1BEF1A9
+
+ # release core1
+ dmi_write_memory 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+$_TARGET1 configure -event examine-start {
+ release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+ $::_TARGET0 arp_poll
+ release_core1
+}
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF40C001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6750-single-core.cfg
b/tcl/target/hpmicro/hpm6750-single-core.cfg
new file mode 100644
index 0000000000..e822b89de6
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6750-single-core.cfg
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6750
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF40C001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6880.cfg b/tcl/target/hpmicro/hpm6880.cfg
new file mode 100644
index 0000000000..107f3e907b
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6880.cfg
@@ -0,0 +1,20 @@
+# Copyright (c) 2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6880
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF410001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6e80-dual-core.cfg
b/tcl/target/hpmicro/hpm6e80-dual-core.cfg
new file mode 100644
index 0000000000..e4ce162498
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6e80-dual-core.cfg
@@ -0,0 +1,66 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set _CHIP hpm6e00
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc dmi_write {reg value} {
+ $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc dmi_read {reg} {
+ set v [$::_TARGET0 riscv dmi_read ${reg}]
+ return ${v}
+}
+proc dmi_write_memory {addr value} {
+ dmi_write 0x39 ${addr}
+ dmi_write 0x3C ${value}
+}
+
+proc dmi_read_memory {addr} {
+ set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
+ dmi_write 0x38 ${sbcs}
+ dmi_write 0x39 ${addr}
+ set value [dmi_read 0x3C]
+ return ${value}
+}
+
+proc release_core1 {} {
+ dmi_write_memory 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+$_TARGET1 configure -event examine-start {
+ release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+ $::_TARGET0 arp_poll
+ release_core1
+}
+
+$_TARGET0 configure -event reset-end {
+ $::_TARGET0 riscv dmi_write 0x39 0xF4002010
+ $::_TARGET0 riscv dmi_write 0x3C 0x2
+}
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF410001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6e80-single-core.cfg
b/tcl/target/hpmicro/hpm6e80-single-core.cfg
new file mode 100644
index 0000000000..745bf5ad19
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6e80-single-core.cfg
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6e00
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000
-work-area-backup 0
+
+targets $_TARGET0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ $::_TARGET0 riscv dmi_write 0x39 0xF410001C
+ $::_TARGET0 riscv dmi_write 0x3C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm_common_csr.cfg
b/tcl/target/hpmicro/hpm_common_csr.cfg
new file mode 100644
index 0000000000..8e24784810
--- /dev/null
+++ b/tcl/target/hpmicro/hpm_common_csr.cfg
@@ -0,0 +1,105 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# expose non-standard csr registers
+# scounteren
+riscv expose_csrs 262
+# mcountinhibit
+riscv expose_csrs 800
+# milmb
+riscv expose_csrs 1984
+# mdlmb
+riscv expose_csrs 1985
+# mecc_code
+riscv expose_csrs 1986
+# mnvec
+riscv expose_csrs 1987
+# mxstatus
+riscv expose_csrs 1988
+# mpft_ctl
+riscv expose_csrs 1989
+# mhsp_ctl
+riscv expose_csrs 1990
+# msp_bound
+riscv expose_csrs 1991
+# msp_base
+riscv expose_csrs 1992
+# mdcause
+riscv expose_csrs 1993
+# mcache_ctl
+riscv expose_csrs 1994
+# mcctlbeginaddr
+riscv expose_csrs 1995
+# mcctlcommand
+riscv expose_csrs 1996
+# mcctldata
+riscv expose_csrs 1997
+# mcounterwen
+riscv expose_csrs 1998
+# mcounterinten
+riscv expose_csrs 1999
+# mmisc_ctl
+riscv expose_csrs 2000
+# mcountermask_m
+riscv expose_csrs 2001
+# mcountermask_s
+riscv expose_csrs 2002
+# mcountermask_u
+riscv expose_csrs 2003
+# mcounterovf
+riscv expose_csrs 2004
+# mslideleg
+riscv expose_csrs 2005
+# mclk_ctl
+riscv expose_csrs 2015
+# dexc2dbg
+riscv expose_csrs 2016
+# ddcause
+riscv expose_csrs 2017
+# uitb
+riscv expose_csrs 2048
+# ucode
+riscv expose_csrs 2049
+# udcause
+riscv expose_csrs 2057
+# ucctlbeginaddr
+riscv expose_csrs 2059
+# ucctlcommand
+riscv expose_csrs 2060
+# slie
+riscv expose_csrs 2500
+# slip
+riscv expose_csrs 2501
+# sdcause
+riscv expose_csrs 2505
+# scctldata
+riscv expose_csrs 2509
+# scounterinten
+riscv expose_csrs 2511
+# scountermask_m
+riscv expose_csrs 2513
+# scountermask_s
+riscv expose_csrs 2514
+# scountermask_u
+riscv expose_csrs 2515
+# scounterovf
+riscv expose_csrs 2516
+# scountinhibit
+riscv expose_csrs 2528
+# shpmevent3
+riscv expose_csrs 2531
+# shpmevent4
+riscv expose_csrs 2532
+# shpmevent5
+riscv expose_csrs 2533
+# shpmevent6
+riscv expose_csrs 2534
+# micm_cfg
+riscv expose_csrs 4032
+# mdcm_cfg
+riscv expose_csrs 4033
+# mmsc_cfg
+riscv expose_csrs 4034
+# mmsc_cfg2
+riscv expose_csrs 4035
+
diff --git a/tcl/target/hpmicro/hpm_common_csr_lite.cfg
b/tcl/target/hpmicro/hpm_common_csr_lite.cfg
new file mode 100644
index 0000000000..a8cec08254
--- /dev/null
+++ b/tcl/target/hpmicro/hpm_common_csr_lite.cfg
@@ -0,0 +1,71 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# expose non-standard csr registers
+# mcountinhibit
+riscv expose_csrs 800
+# milmb
+riscv expose_csrs 1984
+# mdlmb
+riscv expose_csrs 1985
+# mecc_code
+riscv expose_csrs 1986
+# mnvec
+riscv expose_csrs 1987
+# mxstatus
+riscv expose_csrs 1988
+# mpft_ctl
+riscv expose_csrs 1989
+# mhsp_ctl
+riscv expose_csrs 1990
+# msp_bound
+riscv expose_csrs 1991
+# msp_base
+riscv expose_csrs 1992
+# mdcause
+riscv expose_csrs 1993
+# mcache_ctl
+riscv expose_csrs 1994
+# mcctlbeginaddr
+riscv expose_csrs 1995
+# mcctlcommand
+riscv expose_csrs 1996
+# mcctldata
+riscv expose_csrs 1997
+# mcounterwen
+riscv expose_csrs 1998
+# mcounterinten
+riscv expose_csrs 1999
+# mmisc_ctl
+riscv expose_csrs 2000
+# mcountermask_m
+riscv expose_csrs 2001
+# mcountermask_s
+riscv expose_csrs 2002
+# mcountermask_u
+riscv expose_csrs 2003
+# mcounterovf
+riscv expose_csrs 2004
+# dexc2dbg
+riscv expose_csrs 2016
+# ddcause
+riscv expose_csrs 2017
+# uitb
+riscv expose_csrs 2048
+# ucode
+riscv expose_csrs 2049
+# udcause
+riscv expose_csrs 2057
+# ucctlbeginaddr
+riscv expose_csrs 2059
+# ucctlcommand
+riscv expose_csrs 2060
+# micm_cfg
+riscv expose_csrs 4032
+# mdcm_cfg
+riscv expose_csrs 4033
+# mmsc_cfg
+riscv expose_csrs 4034
+# mmsc_cfg2
+riscv expose_csrs 4035
+
--
