This is an automated email from Gerrit. "Ryan QIAN <jianghao.q...@outlook.com>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8725
-- gerrit commit fee5bad0d72b07122bfcabd15f2780fd3dc5d91d Author: Ryan QIAN <jianghao.q...@hpmicro.com> Date: Mon Jan 27 11:47:42 2025 +0800 target/riscv: make sure target is halted when reset_halt is set - some MCU will need certain period of time to be halted after ndmreset is issued, so in deassert_reset, it needs to make sure MCU is halted before clearing DM_DMCONTROL_HALTREQ. Change-Id: Id5171a46cc5d93b83f1915408c725cb9f4c28a4d Signed-off-by: Ryan QIAN <jianghao.q...@hpmicro.com> diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index bb450ce623..f4dab29f7b 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2444,12 +2444,28 @@ static int deassert_reset(struct target *target) target->state = TARGET_HALTED; if (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) { - /* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */ + /* Ack reset with DM_DMCONTROL_HALTREQ for those MCU whose dm needs + * certain period of time to halt after reset is released */ dmi_write(target, DM_DMCONTROL, - set_hartsel(control, index) | + set_hartsel(control_haltreq, index) | DM_DMCONTROL_ACKHAVERESET); } + if (target->reset_halt) { + /* Wait for all harts to halt */ + while (1) { + if (dmi_read(target, &dmstatus, DM_DMSTATUS) != ERROR_OK) { + return ERROR_FAIL; + } + if (get_field(dmstatus, DM_DMSTATUS_ALLHALTED)) + break; + } + } + + /* clear DM_DMCONTROL_HALTREQ */ + dmi_write(target, DM_DMCONTROL, + set_hartsel(control, index)); + if (!target->rtos) break; } --