Hi Antonio, On Qualcomm SoCs, along with the main ARMv8 CPU there exist several other subsystems/cores based on RISC-V, Xtensa and Qualcomm's own Hexagon DSP. Debug access to these cores is provisioned via the main ARM ADIv5/v6 DAP. It appears, currently that there is no provision in the OpenOCD mainline to be able to debug non-ARM sub-systems accessible through the ARM DAP.
For enabling debug of RISC-V cores on QCOM SoCs, we have experimented by making some hacks to the existing OpenOCD code and it is working for us. We, however, are not quite sure whether our approach is right. Would like to get your perspective on (a) whether such configurations for debug of non-ARM cores via the ARM DAP should/would be supported and (b) if yes, what should the approach be Thank you very much. Regards, Agnelo
