This is an automated email from Gerrit. "Tomas Vanek <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9170
-- gerrit commit 6de16f01199b9ac552614f36502d0f9cceda7f3a Author: Tomas Vanek <[email protected]> Date: Mon Oct 13 18:09:27 2025 +0200 target/riscv: implement get_capab() Add support for getting optional capabilities. Change-Id: I8bef0532139f4f9b129c7d56f802347a52c4ee90 Signed-off-by: Tomas Vanek <[email protected]> diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 9da9684e4e..f2713bf096 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -67,6 +67,7 @@ static int register_write_direct(struct target *target, enum gdb_regno number, static int riscv013_access_memory(struct target *target, const struct riscv_mem_access_args args); static bool riscv013_get_impebreak(const struct target *target); static unsigned int riscv013_get_progbufsize(const struct target *target); +static int sba_supports_access(struct target *target, unsigned int size_bytes); enum grouptype { HALT_GROUP, @@ -2246,6 +2247,26 @@ static unsigned int riscv013_data_bits(struct target *target) return 32; } +static unsigned int riscv013_get_capab(struct target *target) +{ + RISCV_INFO(r); + + for (unsigned int i = 0; i < r->num_enabled_mem_access_methods; i++) { + enum riscv_mem_access_method method = r->mem_access_methods[i]; + + if (method == RISCV_MEM_ACCESS_SYSBUS) { + unsigned int bytes = riscv_xlen(target) / 8; + if (sba_supports_access(target, bytes)) { + return TARGET_CAPAB_MEM_READ_WHILE_RUNNING + | TARGET_CAPAB_MEM_WRITE_WHILE_RUNNING + | TARGET_CAPAB_BP_WP_MANIP_AT_ANY_STATE; + } + } + } + + return TARGET_CAPAB_BP_WP_MANIP_AT_ANY_STATE; +} + static COMMAND_HELPER(riscv013_print_info, struct target *target) { RISCV013_INFO(info); @@ -2874,6 +2895,7 @@ static int init_target(struct command_context *cmd_ctx, generic_info->get_dmi_address = &riscv013_get_dmi_address; generic_info->access_memory = &riscv013_access_memory; generic_info->data_bits = &riscv013_data_bits; + generic_info->get_capab = &riscv013_get_capab; generic_info->print_info = &riscv013_print_info; generic_info->get_impebreak = &riscv013_get_impebreak; generic_info->get_progbufsize = &riscv013_get_progbufsize; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 7ef875f805..f7e0b4221d 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -5896,6 +5896,16 @@ static unsigned int riscv_data_bits(struct target *target) return riscv_xlen(target); } +static unsigned int riscv_get_capab(struct target *target) +{ + RISCV_INFO(r); + + if (r->get_capab) + return r->get_capab(target); + + return TARGET_CAPAB_BP_WP_MANIP_AT_ANY_STATE; +} + struct target_type riscv_target = { .name = "riscv", @@ -5943,7 +5953,8 @@ struct target_type riscv_target = { .commands = riscv_command_handlers, .address_bits = riscv_xlen_nonconst, - .data_bits = riscv_data_bits + .data_bits = riscv_data_bits, + .get_capab = riscv_get_capab, }; /*** RISC-V Interface ***/ diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 2a0a9b95f0..b2768352a4 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -306,6 +306,7 @@ struct riscv_info { int (*access_memory)(struct target *target, const struct riscv_mem_access_args args); unsigned int (*data_bits)(struct target *target); + unsigned int (*get_capab)(struct target *target); COMMAND_HELPER((*print_info), struct target *target); --
