This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9762
-- gerrit commit 2a673fbf01f0aba47f0a50c9b42f4eac4ecd2128 Author: Zane Leung <[email protected]> Date: Mon Jun 29 16:04:38 2026 +0200 riscv: move number of idle cycles to struct riscv_dtm Move the fields - riscv011_info_t::dtmcontrol_idle - riscv013_info_t::dtmcs_idle as struct riscv_dtm::idle Change-Id: I70caae72888dd47eb970b9bae76cdd7a8feec276 Signed-off-by: Zane Leung <[email protected]> Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index de33a6a7a6..28d9ee0b12 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -184,10 +184,6 @@ typedef struct { struct memory_cache_line dram_cache[DRAM_CACHE_SIZE]; - /* Number of run-test/idle cycles the target requests we do after each dbus - * access. */ - unsigned int dtmcontrol_idle; - /* This value is incremented every time a dbus access comes back as "busy". * It's used to determine how many run-test/idle cycles to feed the target * in between accesses. */ @@ -334,9 +330,11 @@ static uint32_t idcode_scan(struct target *target) static void increase_dbus_busy_delay(struct target *target) { riscv011_info_t *info = get_info(target); + struct riscv_dtm *dtm = target_to_dtm(target); + info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1; LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d", - info->dtmcontrol_idle, info->dbus_busy_delay, + dtm->idle, info->dbus_busy_delay, info->interrupt_high_delay); dtmcs_scan(target->tap, DTMCONTROL_DBUS_RESET, NULL /* discard value */); @@ -345,9 +343,11 @@ static void increase_dbus_busy_delay(struct target *target) static void increase_interrupt_high_delay(struct target *target) { riscv011_info_t *info = get_info(target); + struct riscv_dtm *dtm = target_to_dtm(target); + info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1; LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d", - info->dtmcontrol_idle, info->dbus_busy_delay, + dtm->idle, info->dbus_busy_delay, info->interrupt_high_delay); } @@ -377,7 +377,7 @@ static void add_dbus_scan(const struct target *target, struct scan_field *field, jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE); - int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay; + int idle_count = dtm->idle + info->dbus_busy_delay; if (data & DMCONTROL_INTERRUPT) idle_count += info->interrupt_high_delay; @@ -443,7 +443,7 @@ static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in, /* Assume dbus is already selected. */ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE); - int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay; + int idle_count = dtm->idle + info->dbus_busy_delay; if (idle_count) jtag_add_runtest(idle_count, TAP_IDLE); @@ -1516,12 +1516,12 @@ static int examine(struct target *target) riscv011_info_t *info = get_info(target); dtm->abits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS); - info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE); - if (info->dtmcontrol_idle == 0) { + dtm->idle = get_field(dtmcontrol, DTMCONTROL_IDLE); + if (dtm->idle == 0) { /* Some old SiFive cores don't set idle but need it to be 1. */ uint32_t idcode = idcode_scan(target); if (idcode == 0x10e31913) - info->dtmcontrol_idle = 1; + dtm->idle = 1; } uint32_t dminfo = dbus_read(target, DMINFO); diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 4959f1145e..961cdc8837 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -222,10 +222,6 @@ typedef struct { /* We only need the address so that we know the alignment of the buffer. */ riscv_addr_t progbuf_address; - /* Number of run-test/idle cycles the target requests we do after each dbus - * access. */ - unsigned int dtmcs_idle; - /* This structure is used to determine how many run-test/idle to use after * an access of corresponding "riscv_scan_delay_class". * Values are incremented every time an access results in a busy @@ -2054,7 +2050,7 @@ static int examine(struct target *target) info->index = target->coreid; dtm->abits = get_field(dtmcontrol, DTM_DTMCS_ABITS); - info->dtmcs_idle = get_field(dtmcontrol, DTM_DTMCS_IDLE); + dtm->idle = get_field(dtmcontrol, DTM_DTMCS_IDLE); if (dtm->abits > RISCV013_DTMCS_ABITS_MAX) { /* Max. address width given by the debug specification is exceeded */ diff --git a/src/target/riscv/riscv_dtm.h b/src/target/riscv/riscv_dtm.h index 9bafb15eeb..0191f8556c 100644 --- a/src/target/riscv/riscv_dtm.h +++ b/src/target/riscv/riscv_dtm.h @@ -9,6 +9,10 @@ struct target; struct riscv_dtm { /* Number of address bits in the dbus register. */ unsigned int abits; + + /* Number of run-test/idle cycles the target requests we do after each dbus + * access. */ + unsigned int idle; }; struct riscv_dtm *target_to_dtm(const struct target *target); --
