This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9765
-- gerrit commit 91ff11f2d4164c8caa0215a1adf7379549f43376 Author: Zane Leung <[email protected]> Date: Mon Jun 29 16:28:50 2026 +0200 riscv: move reset_delays_wait to struct riscv_dtm Move the field struct riscv_info::reset_delays_wait as struct riscv_dtm::reset_delays_wait Change-Id: Ib87dc12843cffea2bbb60f95e523722b661e61e1 Signed-off-by: Zane Leung <[email protected]> Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 5f6f52bcb5..6ad5ba83d5 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -342,12 +342,11 @@ static void add_dbus_scan(const struct target *target, struct scan_field *field, uint8_t *out_value, uint8_t *in_value, dbus_op_t op, uint16_t address, uint64_t data) { - RISCV_INFO(r); struct riscv_dtm *dtm = target_to_dtm(target); - if (r->reset_delays_wait >= 0) { - r->reset_delays_wait--; - if (r->reset_delays_wait < 0) { + if (dtm->reset_delays_wait >= 0) { + dtm->reset_delays_wait--; + if (dtm->reset_delays_wait < 0) { dtm->dbus_busy_delay = 0; dtm->interrupt_high_delay = 0; } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 961cdc8837..bcaae0d4b4 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -453,16 +453,17 @@ static void reset_learned_delays(struct target *target) static void decrement_reset_delays_counter(struct target *target, size_t finished_scans) { - RISCV_INFO(r); - if (r->reset_delays_wait < 0) { - assert(r->reset_delays_wait == -1); + struct riscv_dtm *dtm = target_to_dtm(target); + + if (dtm->reset_delays_wait < 0) { + assert(dtm->reset_delays_wait == -1); return; } - if ((size_t)r->reset_delays_wait >= finished_scans) { - r->reset_delays_wait -= finished_scans; + if ((size_t)dtm->reset_delays_wait >= finished_scans) { + dtm->reset_delays_wait -= finished_scans; return; } - r->reset_delays_wait = -1; + dtm->reset_delays_wait = -1; LOG_TARGET_DEBUG(target, "resetting learned delays (reset_delays_wait counter expired)"); reset_learned_delays(target); @@ -2542,13 +2543,13 @@ static int sb_write_address(struct target *target, target_addr_t address, static int batch_run(struct target *target, struct riscv_batch *batch) { - RISCV_INFO(r); + struct riscv_dtm *dtm = target_to_dtm(target); RISCV013_INFO(info); select_dmi(target->tap); riscv_batch_add_nop(batch); const int result = riscv_batch_run_from(batch, 0, &info->learned_delays, - /*resets_delays*/ r->reset_delays_wait >= 0, - r->reset_delays_wait); + /*resets_delays*/ dtm->reset_delays_wait >= 0, + dtm->reset_delays_wait); if (result != ERROR_OK) return result; /* TODO: To use `riscv_batch_finished_scans()` here, it is needed for @@ -2566,6 +2567,7 @@ static int batch_run(struct target *target, struct riscv_batch *batch) */ static int batch_run_timeout(struct target *target, struct riscv_batch *batch) { + struct riscv_dtm *dtm = target_to_dtm(target); RISCV013_INFO(info); select_dmi(target->tap); riscv_batch_add_nop(batch); @@ -2576,11 +2578,10 @@ static int batch_run_timeout(struct target *target, struct riscv_batch *batch) RISCV_DELAY_BASE); int result; do { - RISCV_INFO(r); result = riscv_batch_run_from(batch, finished_scans, &info->learned_delays, - /*resets_delays*/ r->reset_delays_wait >= 0, - r->reset_delays_wait); + /*resets_delays*/ dtm->reset_delays_wait >= 0, + dtm->reset_delays_wait); if (result != ERROR_OK) return result; const size_t new_finished_scans = riscv_batch_finished_scans(batch); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 30094b34b5..6f79648e98 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -665,8 +665,10 @@ static int riscv_init_target(struct command_context *cmd_ctx, { LOG_TARGET_DEBUG(target, "riscv_init_target()"); RISCV_INFO(info); + struct riscv_dtm *dtm = target_to_dtm(target); + info->cmd_ctx = cmd_ctx; - info->reset_delays_wait = -1; + dtm->reset_delays_wait = -1; select_dtmcontrol.num_bits = target->tap->ir_length; select_dbus.num_bits = target->tap->ir_length; @@ -4795,8 +4797,8 @@ COMMAND_HANDLER(riscv_reset_delays) COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait); struct target *target = get_current_target(CMD_CTX); - RISCV_INFO(r); - r->reset_delays_wait = wait; + struct riscv_dtm *dtm = target_to_dtm(target); + dtm->reset_delays_wait = wait; return ERROR_OK; } diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 4ae0ba851c..1f78f76c6c 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -228,10 +228,6 @@ struct riscv_info { bool triggers_enumerated; - /* Decremented every scan, and when it reaches 0 we clear the learned - * delays, causing them to be relearned. Used for testing. */ - int reset_delays_wait; - /* This target has been prepped and is ready to step/resume. */ bool prepped; /* This target was selected using hasel. */ diff --git a/src/target/riscv/riscv_dtm.h b/src/target/riscv/riscv_dtm.h index e51d5a2d2c..3027c0f12d 100644 --- a/src/target/riscv/riscv_dtm.h +++ b/src/target/riscv/riscv_dtm.h @@ -14,6 +14,10 @@ struct riscv_dtm { * access. */ unsigned int idle; + /* Decremented every scan, and when it reaches 0 we clear the learned + * delays, causing them to be relearned. Used for testing. */ + int reset_delays_wait; + /* This value is incremented every time a dbus access comes back as "busy". * It's used to determine how many run-test/idle cycles to feed the target * in between accesses. */ --
