This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9766
-- gerrit commit bb7e14e3b6ada805384aed75a46bf8bed9d7566d Author: Zane Leung <[email protected]> Date: Mon Jun 29 17:06:22 2026 +0200 riscv: move learned_delays to struct riscv_dtm Move the field struct riscv_info::learned_delays as struct riscv_dtm::learned_delays Change-Id: Ic2ce3fed0245db044df097d264c037fef81260bf Signed-off-by: Zane Leung <[email protected]> Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/riscv/batch.h b/src/target/riscv/batch.h index 5d8b57234e..d151206d99 100644 --- a/src/target/riscv/batch.h +++ b/src/target/riscv/batch.h @@ -54,13 +54,6 @@ riscv_scan_delay_class_name(enum riscv_scan_delay_class delay_class) */ #define RISCV_SCAN_DELAY_MAX (INT_MAX / 2) -struct riscv_scan_delays { - unsigned int base_delay; - unsigned int ac_delay; - unsigned int sb_read_delay; - unsigned int sb_write_delay; -}; - static inline unsigned int riscv_scan_get_delay(const struct riscv_scan_delays *delays, enum riscv_scan_delay_class delay_class) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index bcaae0d4b4..87c160dfee 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -222,13 +222,6 @@ typedef struct { /* We only need the address so that we know the alignment of the buffer. */ riscv_addr_t progbuf_address; - /* This structure is used to determine how many run-test/idle to use after - * an access of corresponding "riscv_scan_delay_class". - * Values are incremented every time an access results in a busy - * response. - */ - struct riscv_scan_delays learned_delays; - struct ac_cache ac_not_supported_cache; /* Some fields from hartinfo. */ @@ -434,21 +427,21 @@ static void select_dmi(struct jtag_tap *tap) static int increase_dmi_busy_delay(struct target *target) { - RISCV013_INFO(info); + struct riscv_dtm *dtm = target_to_dtm(target); int res = dtmcs_scan(target->tap, DTM_DTMCS_DMIRESET, NULL /* discard result */); if (res != ERROR_OK) return res; - return riscv_scan_increase_delay(&info->learned_delays, RISCV_DELAY_BASE); + return riscv_scan_increase_delay(&dtm->learned_delays, RISCV_DELAY_BASE); } static void reset_learned_delays(struct target *target) { - RISCV013_INFO(info); - assert(info); - memset(&info->learned_delays, 0, sizeof(info->learned_delays)); + struct riscv_dtm *dtm = target_to_dtm(target); + + memset(&dtm->learned_delays, 0, sizeof(dtm->learned_delays)); } static void decrement_reset_delays_counter(struct target *target, size_t finished_scans) @@ -616,8 +609,9 @@ static int dmstatus_read(struct target *target, uint32_t *dmstatus, static int increase_ac_busy_delay(struct target *target) { - riscv013_info_t *info = get_info(target); - return riscv_scan_increase_delay(&info->learned_delays, + struct riscv_dtm *dtm = target_to_dtm(target); + + return riscv_scan_increase_delay(&dtm->learned_delays, RISCV_DELAY_ABSTRACT_COMMAND); } @@ -2544,10 +2538,9 @@ static int sb_write_address(struct target *target, target_addr_t address, static int batch_run(struct target *target, struct riscv_batch *batch) { struct riscv_dtm *dtm = target_to_dtm(target); - RISCV013_INFO(info); select_dmi(target->tap); riscv_batch_add_nop(batch); - const int result = riscv_batch_run_from(batch, 0, &info->learned_delays, + const int result = riscv_batch_run_from(batch, 0, &dtm->learned_delays, /*resets_delays*/ dtm->reset_delays_wait >= 0, dtm->reset_delays_wait); if (result != ERROR_OK) @@ -2568,18 +2561,17 @@ static int batch_run(struct target *target, struct riscv_batch *batch) static int batch_run_timeout(struct target *target, struct riscv_batch *batch) { struct riscv_dtm *dtm = target_to_dtm(target); - RISCV013_INFO(info); select_dmi(target->tap); riscv_batch_add_nop(batch); size_t finished_scans = 0; int64_t then = timeval_ms() + 1000 * riscv_get_command_timeout_sec(); - const unsigned int old_base_delay = riscv_scan_get_delay(&info->learned_delays, + const unsigned int old_base_delay = riscv_scan_get_delay(&dtm->learned_delays, RISCV_DELAY_BASE); int result; do { result = riscv_batch_run_from(batch, finished_scans, - &info->learned_delays, + &dtm->learned_delays, /*resets_delays*/ dtm->reset_delays_wait >= 0, dtm->reset_delays_wait); if (result != ERROR_OK) @@ -2604,7 +2596,7 @@ static int batch_run_timeout(struct target *target, struct riscv_batch *batch) LOG_TARGET_DEBUG(target, "%s delay is restored to %u.", riscv_scan_delay_class_name(RISCV_DELAY_BASE), old_base_delay); - riscv_scan_set_delay(&info->learned_delays, RISCV_DELAY_BASE, + riscv_scan_set_delay(&dtm->learned_delays, RISCV_DELAY_BASE, old_base_delay); LOG_TARGET_ERROR(target, "DMI operation didn't complete in %d seconds. " @@ -2638,6 +2630,7 @@ static int sample_memory_bus_v1(struct target *target, const riscv_sample_config_t *config, int64_t until_ms) { + struct riscv_dtm *dtm = target_to_dtm(target); RISCV013_INFO(info); unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); if (sbasize == 0 || sbasize > 64) { @@ -2757,7 +2750,7 @@ static int sample_memory_bus_v1(struct target *target, /* Discard this batch when we encounter "busy error" state on the System Bus level. * We'll try next time with a larger System Bus read delay. */ dm_write(target, DM_SBCS, sbcs_read | DM_SBCS_SBBUSYERROR | DM_SBCS_SBERROR); - int res = riscv_scan_increase_delay(&info->learned_delays, + int res = riscv_scan_increase_delay(&dtm->learned_delays, RISCV_DELAY_SYSBUS_READ); riscv_batch_free(batch); if (res != ERROR_OK) @@ -2987,6 +2980,7 @@ static bool dcsr_ebreak_config_equals_reset_value(const struct target *target) static int deassert_reset(struct target *target) { + struct riscv_dtm *dtm = target_to_dtm(target); RISCV013_INFO(info); dm013_info_t *dm = get_dm(target); if (!dm) @@ -3013,7 +3007,7 @@ static int deassert_reset(struct target *target) return result; uint32_t dmstatus; - const unsigned int orig_base_delay = riscv_scan_get_delay(&info->learned_delays, + const unsigned int orig_base_delay = riscv_scan_get_delay(&dtm->learned_delays, RISCV_DELAY_BASE); int64_t then = timeval_ms() + 1000 * riscv_get_command_timeout_sec(); LOG_TARGET_DEBUG(target, "Waiting for hart to come out of reset."); @@ -3033,7 +3027,7 @@ static int deassert_reset(struct target *target) } } while (!get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)); - riscv_scan_set_delay(&info->learned_delays, RISCV_DELAY_BASE, + riscv_scan_set_delay(&dtm->learned_delays, RISCV_DELAY_BASE, orig_base_delay); /* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */ @@ -3401,7 +3395,7 @@ static int read_memory_bus_v1(struct target *target, const struct riscv_mem_acce if (!dm) return ERROR_FAIL; - RISCV013_INFO(info); + struct riscv_dtm *dtm = target_to_dtm(target); target_addr_t next_address = address; target_addr_t end_address = address + (increment ? count : 1) * size; @@ -3503,7 +3497,7 @@ static int read_memory_bus_v1(struct target *target, const struct riscv_mem_acce return ERROR_FAIL; } - int res = riscv_scan_increase_delay(&info->learned_delays, + int res = riscv_scan_increase_delay(&dtm->learned_delays, RISCV_DELAY_SYSBUS_READ); if (res != ERROR_OK) return res; @@ -4700,7 +4694,7 @@ static int write_memory_bus_v1(struct target *target, const struct riscv_mem_acc { assert(riscv_mem_access_is_write(args)); - RISCV013_INFO(info); + struct riscv_dtm *dtm = target_to_dtm(target); uint32_t sbcs = sb_sbaccess(args.size); sbcs = set_field(sbcs, DM_SBCS_SBAUTOINCREMENT, 1); dm_write(target, DM_SBCS, sbcs); @@ -4787,7 +4781,7 @@ static int write_memory_bus_v1(struct target *target, const struct riscv_mem_acc /* Slow down before trying again. * FIXME: Possible overflow is ignored here. */ - riscv_scan_increase_delay(&info->learned_delays, + riscv_scan_increase_delay(&dtm->learned_delays, RISCV_DELAY_SYSBUS_WRITE); } diff --git a/src/target/riscv/riscv_dtm.h b/src/target/riscv/riscv_dtm.h index 3027c0f12d..15dc86ddac 100644 --- a/src/target/riscv/riscv_dtm.h +++ b/src/target/riscv/riscv_dtm.h @@ -5,6 +5,13 @@ struct target; +struct riscv_scan_delays { + unsigned int base_delay; + unsigned int ac_delay; + unsigned int sb_read_delay; + unsigned int sb_write_delay; +}; + /* This represents an RISC-V Debug Transport Module (DTM) */ struct riscv_dtm { /* Number of address bits in the dbus register. */ @@ -28,6 +35,13 @@ struct riscv_dtm { * interrupt high, so ideally we never have to perform a whole extra scan * before the interrupt is cleared. */ unsigned int interrupt_high_delay; + + /* This structure is used to determine how many run-test/idle to use after + * an access of corresponding "riscv_scan_delay_class". + * Values are incremented every time an access results in a busy + * response. + */ + struct riscv_scan_delays learned_delays; }; struct riscv_dtm *target_to_dtm(const struct target *target); --
