On Tue, 19 Aug 2008, Daniel Gimpelevich wrote: > On Tue, 19 Aug 2008 09:10:19 +0200, Øyvind Harboe wrote: > > > I guess there is no royal road to solving this problem... There is a lot > > of necessary complexity to the situation that just need to be grokked. > > Yes, and so far, nobody involved seems to have sufficient knowledge or > ideas to solve the problem, with the possible exception of Nicolas Pitre. > I am hoping he can weigh in.
So far I've always been able to halt a Feroceon based board with no flash content simply by holding the reset button while performing a halt on the openocd console then quickly releasing the reset button. It seems that the processor will happily halt right on the reset vector at that point if DBGRQ is already asserted when it attempts to execute the very first instruction after a reset. The same should be doable by asserting the SRST signal but often the JTAG cable (or the board design) doesn't route it properly if at all. Nicolas
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