On Tue, 19 Aug 2008, Øyvind Harboe wrote: > On Tue, Aug 19, 2008 at 4:47 PM, Nicolas Pitre <[EMAIL PROTECTED]> wrote: > > On Tue, 19 Aug 2008, Daniel Gimpelevich wrote: > > > >> On Tue, 19 Aug 2008 09:10:19 +0200, Øyvind Harboe wrote: > >> > >> > I guess there is no royal road to solving this problem... There is a lot > >> > of necessary complexity to the situation that just need to be grokked. > >> > >> Yes, and so far, nobody involved seems to have sufficient knowledge or > >> ideas to solve the problem, with the possible exception of Nicolas Pitre. > >> I am hoping he can weigh in. > > > > So far I've always been able to halt a Feroceon based board with no > > flash content simply by holding the reset button while performing a halt > > on the openocd console then quickly releasing the reset button. > > Does the reset button affect anything but trst & srst?
Normally, SRST and the reset button should be the same. TRST is separate and affects only the debug interface logic. On some boards I have here, nTRST is pulled low permanently and needs to have VCC applied to it for the debug logic to operate (jumper required with those JTAG cables without TRST signal). > > It > > seems that the processor will happily halt right on the reset vector at > > that point if DBGRQ is already asserted when it attempts to execute the > > very first instruction after a reset. > > DBGRQ as in the cable? DBGRQ as in bit 1 of the debug control register within the EICE logic block. > type "help dbgrq" in OpenOCD and you should get help on the config > option... Here I mean the "arm7_9 dbgrq" option. Nicolas
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