Edwin Olson wrote:
> I'm using an lm3s6965-ek as a JTAG interface and a custom board with a
> lm3s8962 as a debug target. I'm running fedora linux 9 with libftdi.
>
> When I attempt to write my program to flash, the first attempt seems to
> consistently result in only an erased flash (all ff's.) A second attempt
> always seems to works. I'm running from openocd HEAD, but this problem
> has been happening (at least intermittently) since revision 500 or so.
> You'll also note BUG() firing periodically, though I'm not sure its
> relevant to what's happening here.
I can reproduce that, but I have some more problems to add. My setup is:
- Luminary RDK-IDM board, with a LM3S6918 CPU.
http://www.luminarymicro.com/products/rdk-idm.html
- openocd from svn head (pulled some weeks ago)
- parallel port wiggler2 adapter
I have tried two possible configurations:
target cortex_m3 little 0 lm3s
and
target cortex_m3 little 0
Both show different behaviour, but none of the two yields a fully working setup.
Using "target cortex_m3 little 0 lm3s" (which I assume should be the right one
for the CPU) I can reset the CPU and erase/program the flash. However, both
"reset run" and "reset halt" followed by "resume" do *not* run the program in
flash. OpenOCD thinks the target is running, but nothing happens on the display
or serial port.
Using "target cortex_m3 little 0", "reset run", "resume", singlestepping etc.
work fine. However, if the flash is erased, reset halt does not get control of
the chip, and I can't re-program the flash. In that situation, I have to switch
to the "lm3s" config which *can* program the flash, but is useless for
debugging/running the application.
Using both configuration variants, most of the time, the first flash command
fails as described above, while a second try succeeds. This is annoying, but
not really critical.
Using both configuration variants, I am not able to reset the CPU directly out
of reset - the program runs several commands before openocd gains control of
the target, which may also cause the problems when the flash is empty.
I have attached -d3 logs of both configuration cases, with an application in
flash, as well as one variant of my rdk-idm.cfg.
cu
Michael
using
target cortex_m3 little 0 lm3s
Script started on Sun Aug 24 20:30:41 2008
$ openocd -d3 -f wiggler2.cfg -f rdk-idm.cfg
Open On-Chip Debugger 1.0 (2008-08-01-20:44) svn:885M
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
Debug: 4 1 configuration.c:88 find_file(): found /home/rincewind/.openocd/wiggler2.cfg
Debug: 6 1 command.c:78 script_command(): script_command - interface
Debug: 7 1 command.c:95 script_command(): script_command - interface, argv[0]=ocd_interface
Debug: 8 1 command.c:95 script_command(): script_command - interface, argv[1]=parport
Debug: 10 1 command.c:78 script_command(): script_command - parport_port
Debug: 11 1 command.c:95 script_command(): script_command - parport_port, argv[0]=ocd_parport_port
Debug: 12 1 command.c:95 script_command(): script_command - parport_port, argv[1]=0
Debug: 14 1 command.c:78 script_command(): script_command - parport_cable
Debug: 15 1 command.c:95 script_command(): script_command - parport_cable, argv[0]=ocd_parport_cable
Debug: 16 1 command.c:95 script_command(): script_command - parport_cable, argv[1]=wiggler2
Debug: 18 1 command.c:78 script_command(): script_command - jtag_speed
Debug: 19 1 command.c:95 script_command(): script_command - jtag_speed, argv[0]=ocd_jtag_speed
Debug: 20 1 command.c:95 script_command(): script_command - jtag_speed, argv[1]=0
Debug: 21 1 jtag.c:1880 handle_jtag_speed_command(): handle jtag speed
User: 22 1 command.c:359 command_print(): jtag_speed: 0
Debug: 23 2 configuration.c:88 find_file(): found /home/rincewind/.openocd/rdk-idm.cfg
Debug: 25 2 command.c:78 script_command(): script_command - jtag_nsrst_delay
Debug: 26 2 command.c:95 script_command(): script_command - jtag_nsrst_delay, argv[0]=ocd_jtag_nsrst_delay
Debug: 27 2 command.c:95 script_command(): script_command - jtag_nsrst_delay, argv[1]=150
Debug: 29 2 command.c:78 script_command(): script_command - jtag_ntrst_delay
Debug: 30 2 command.c:95 script_command(): script_command - jtag_ntrst_delay, argv[0]=ocd_jtag_ntrst_delay
Debug: 31 2 command.c:95 script_command(): script_command - jtag_ntrst_delay, argv[1]=150
Debug: 33 2 command.c:78 script_command(): script_command - reset_config
Debug: 34 2 command.c:95 script_command(): script_command - reset_config, argv[0]=ocd_reset_config
Debug: 35 2 command.c:95 script_command(): script_command - reset_config, argv[1]=trst_and_srst
Debug: 37 2 command.c:78 script_command(): script_command - jtag_device
Debug: 38 2 command.c:95 script_command(): script_command - jtag_device, argv[0]=ocd_jtag_device
Debug: 39 2 command.c:95 script_command(): script_command - jtag_device, argv[1]=4
Debug: 40 2 command.c:95 script_command(): script_command - jtag_device, argv[2]=0x1
Debug: 41 2 command.c:95 script_command(): script_command - jtag_device, argv[3]=0xf
Debug: 42 2 command.c:95 script_command(): script_command - jtag_device, argv[4]=0xe
Debug: 44 2 command.c:78 script_command(): script_command - target
Debug: 45 2 command.c:95 script_command(): script_command - target, argv[0]=ocd_target
Debug: 46 3 command.c:95 script_command(): script_command - target, argv[1]=cortex_m3
Debug: 47 3 command.c:95 script_command(): script_command - target, argv[2]=little
Debug: 48 3 command.c:95 script_command(): script_command - target, argv[3]=0
Debug: 49 3 command.c:95 script_command(): script_command - target, argv[4]=lm3s
Debug: 51 3 command.c:78 script_command(): script_command - working_area
Debug: 52 3 command.c:95 script_command(): script_command - working_area, argv[0]=ocd_working_area
Debug: 53 3 command.c:95 script_command(): script_command - working_area, argv[1]=0
Debug: 54 3 command.c:95 script_command(): script_command - working_area, argv[2]=0x20000000
Debug: 55 3 command.c:95 script_command(): script_command - working_area, argv[3]=0x4000
Debug: 56 3 command.c:95 script_command(): script_command - working_area, argv[4]=nobackup
Debug: 58 3 command.c:78 script_command(): script_command - bank
Debug: 59 3 command.c:95 script_command(): script_command - bank, argv[0]=ocd_flash_bank
Debug: 60 3 command.c:95 script_command(): script_command - bank, argv[1]=stellaris
Debug: 61 3 command.c:95 script_command(): script_command - bank, argv[2]=0
Debug: 62 3 command.c:95 script_command(): script_command - bank, argv[3]=0
Debug: 63 3 command.c:95 script_command(): script_command - bank, argv[4]=0
Debug: 64 3 command.c:95 script_command(): script_command - bank, argv[5]=0
Debug: 65 3 command.c:95 script_command(): script_command - bank, argv[6]=0
Debug: 67 4 command.c:78 script_command(): script_command - init
Debug: 68 4 command.c:95 script_command(): script_command - init, argv[0]=ocd_init
Debug: 69 4 openocd.c:91 handle_init_command(): target init complete
Debug: 70 4 parport.c:349 parport_init(): opening /dev/parport0...
Debug: 71 4 parport.c:361 parport_init(): ...open
Debug: 72 45 parport.c:233 parport_reset(): trst: 0, srst: 0
Debug: 73 45 openocd.c:98 handle_init_command(): jtag interface init complete
Debug: 74 45 jtag.c:1558 jtag_init_inner(): Init JTAG chain
Debug: 75 45 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 76 45 jtag.c:1296 jtag_reset_callback(): -
Debug: 77 45 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 78 45 jtag.c:1296 jtag_reset_callback(): -
Info: 79 49 jtag.c:1413 jtag_examine_chain(): JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
Debug: 80 49 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 81 49 jtag.c:1296 jtag_reset_callback(): -
Debug: 82 50 openocd.c:104 handle_init_command(): jtag init complete
Debug: 83 50 cortex_swjdp.c:946 ahbap_debugport_init():
Debug: 84 57 cortex_swjdp.c:990 ahbap_debugport_init(): AHB-AP ID Register 0x14770011, Debug ROM Address 0xe00ff003
Debug: 85 59 target.c:1102 target_read_u32(): address: 0xe000ed00, value: 0x411fc231
Debug: 86 60 cortex_m3.c:1336 cortex_m3_examine(): CORTEX-M3 processor detected
Debug: 87 60 cortex_m3.c:1337 cortex_m3_examine(): cpuid: 0x411fc231
Debug: 88 61 target.c:1102 target_read_u32(): address: 0xe000e004, value: 0x00000001
Debug: 89 63 target.c:1102 target_read_u32(): address: 0xe000e100, value: 0x01020000
Debug: 90 63 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[0] = 0x01020000
Debug: 91 65 target.c:1102 target_read_u32(): address: 0xe000e104, value: 0x00000000
Debug: 92 67 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[1] = 0x00000000
Debug: 93 69 target.c:1102 target_read_u32(): address: 0xe0002000, value: 0x00000261
Debug: 94 69 cortex_m3.c:1360 cortex_m3_examine(): FPB fpcr 0x261, numcode 6, numlit 2
Debug: 95 71 target.c:1102 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 96 71 openocd.c:107 handle_init_command(): jtag examine complete
Debug: 97 72 openocd.c:113 handle_init_command(): flash init complete
Debug: 98 72 openocd.c:117 handle_init_command(): NAND init complete
Debug: 99 72 openocd.c:121 handle_init_command(): pld init complete
Warning: 100 72 telnet_server.c:627 telnet_init(): no telnet port specified, using default port 4444
Warning: 101 72 gdb_server.c:2019 gdb_init(): no gdb port specified, using default port 3333
Debug: 102 72 gdb_server.c:2034 gdb_init(): gdb service for target cortex_m3 at port 3333
Warning: 103 72 tcl_server.c:178 tcl_init(): no tcl port specified, using default port 6666
Info: 104 4823 server.c:81 add_connection(): accepting 'telnet' connection from 0
Debug: 106 7414 command.c:78 script_command(): script_command - reset
Debug: 107 7414 command.c:95 script_command(): script_command - reset, argv[0]=ocd_reset
Debug: 108 7414 command.c:95 script_command(): script_command - reset, argv[1]=halt
Debug: 109 7414 jtag.c:1602 jtag_init_reset(): Trying to bring the JTAG controller to life by asserting TRST / TLR
Debug: 110 7414 jtag.c:998 jtag_add_reset(): SRST line released
Debug: 111 7414 jtag.c:1017 jtag_add_reset(): TRST line asserted
Debug: 112 7414 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 113 7414 jtag.c:1296 jtag_reset_callback(): -
Debug: 114 7414 jtag.c:994 jtag_add_reset(): SRST line asserted
Debug: 115 7414 jtag.c:1017 jtag_add_reset(): TRST line asserted
Debug: 116 7414 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 117 7414 jtag.c:1296 jtag_reset_callback(): -
Debug: 118 7414 jtag.c:994 jtag_add_reset(): SRST line asserted
Debug: 119 7414 jtag.c:998 jtag_add_reset(): SRST line released
Debug: 120 7414 parport.c:233 parport_reset(): trst: 1, srst: 0
Debug: 121 7564 parport.c:233 parport_reset(): trst: 1, srst: 1
Debug: 122 7564 parport.c:233 parport_reset(): trst: 0, srst: 1
Debug: 123 7715 parport.c:233 parport_reset(): trst: 0, srst: 0
Debug: 124 8015 jtag.c:1558 jtag_init_inner(): Init JTAG chain
Debug: 125 8015 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 126 8015 jtag.c:1296 jtag_reset_callback(): -
Info: 127 8018 jtag.c:1413 jtag_examine_chain(): JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
Debug: 128 8019 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 129 8019 jtag.c:1296 jtag_reset_callback(): -
Debug: 131 8019 cortex_swjdp.c:946 ahbap_debugport_init():
Debug: 132 8025 cortex_swjdp.c:990 ahbap_debugport_init(): AHB-AP ID Register 0x14770011, Debug ROM Address 0xe00ff003
Debug: 133 8027 target.c:1102 target_read_u32(): address: 0xe000ed00, value: 0x411fc231
Debug: 134 8027 cortex_m3.c:1336 cortex_m3_examine(): CORTEX-M3 processor detected
Debug: 135 8027 cortex_m3.c:1337 cortex_m3_examine(): cpuid: 0x411fc231
Debug: 136 8029 target.c:1102 target_read_u32(): address: 0xe000e004, value: 0x00000001
Debug: 137 8031 target.c:1102 target_read_u32(): address: 0xe000e100, value: 0x00020000
Debug: 138 8031 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[0] = 0x00020000
Debug: 139 8033 target.c:1102 target_read_u32(): address: 0xe000e104, value: 0x00000000
Debug: 140 8033 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[1] = 0x00000000
Debug: 141 8034 target.c:1102 target_read_u32(): address: 0xe0002000, value: 0x00000260
Debug: 142 8034 cortex_m3.c:1360 cortex_m3_examine(): FPB fpcr 0x260, numcode 6, numlit 2
Debug: 143 8036 target.c:1102 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 144 8036 cortex_m3.c:679 cortex_m3_assert_reset(): target->state: unknown
Debug: 145 8042 target.c:1102 target_read_u32(): address: 0x400fe000, value: 0x10010002
Warning: 146 8044 jtag.c:1212 jtag_check_value(): value captured during scan didn't pass the requested check: captured: 0x00 check_value: 0x01 check_mask: 0x0f
Warning: 147 8044 jtag.c:1172 jtag_read_buffer(): in_handler reported a failed check
Warning: 148 8045 cortex_swjdp.c:196 swjdp_transaction_endcheck(): Invalid ACK in SWJDP transaction
Debug: 149 8045 cortex_m3.c:762 cortex_m3_assert_reset(): Using Luminary Reset: SYSRESETREQ
Debug: 150 8095 cortex_m3.c:452 cortex_m3_halt(): target->state: reset
Debug: 151 8095 cortex_m3.c:775 cortex_m3_deassert_reset(): target->state: reset
Debug: 152 8096 jtag.c:998 jtag_add_reset(): SRST line released
Debug: 153 8096 parport.c:233 parport_reset(): trst: 0, srst: 0
Debug: 154 8398 cortex_m3.c:404 cortex_m3_poll(): Exit from reset with dcb_dhcsr 0x411fc231
Debug: 155 8400 cortex_m3.c:179 cortex_m3_endreset_event(): DCB_DEMCR = 0xfa050000
Debug: 156 8402 target.c:1170 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 157 8405 target.c:1170 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 158 8406 target.c:1170 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 159 8408 target.c:1170 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 160 8409 target.c:1170 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 161 8411 target.c:1170 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 162 8413 target.c:1170 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 163 8414 target.c:1170 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 164 8415 target.c:1170 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 165 8417 target.c:1170 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 166 8418 target.c:1170 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 167 8420 target.c:1170 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 168 8422 target.c:1170 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 169 8423 target.c:1170 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 170 8425 target.c:1170 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 171 8426 target.c:1170 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 172 8428 target.c:1170 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 173 8429 target.c:1170 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 174 8431 target.c:1170 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 175 8432 target.c:1170 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 176 8434 target.c:1170 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 177 8436 cortex_m3.c:303 cortex_m3_debug_entry():
Debug: 178 8440 cortex_m3.c:111 cortex_m3_clear_halt(): NVIC_DFSR 0x8
Debug: 179 8447 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 0 value 0x5010
Debug: 180 8451 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 1 value 0x0
Debug: 181 8456 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 2 value 0x400043fc
Debug: 182 8461 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 3 value 0x400053fc
Debug: 183 8465 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 4 value 0x73
Debug: 184 8470 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 5 value 0x69
Debug: 185 8475 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 6 value 0xc618
Debug: 186 8479 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 7 value 0x0
Debug: 187 8484 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 8 value 0x5bec
Debug: 188 8489 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 9 value 0x0
Debug: 189 8493 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 10 value 0x14
Debug: 190 8498 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 11 value 0xb
Debug: 191 8503 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 12 value 0x1
Debug: 192 8507 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 13 value 0x200013a4
Debug: 193 8512 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 14 value 0xffffffff
Debug: 194 8517 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 15 value 0x1128
Debug: 195 8522 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 16 value 0x1000000
Debug: 196 8527 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 17 value 0x200013a4
Debug: 197 8532 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 18 value 0x15004240
Debug: 198 8537 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 19 value 0x0
Debug: 199 8542 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 20 value 0x0
Debug: 200 8548 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 21 value 0x0
Debug: 201 8552 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 22 value 0x0
Debug: 202 8552 cortex_m3.c:363 cortex_m3_debug_entry(): entered debug state in core mode: Thread at PC 0x1128, target->state: halted
Debug: 203 8552 target.c:639 target_call_event_callbacks(): target event 0
User: 204 8552 target.c:875 target_arch_state(): target state: halted
User: 205 8553 armv7m.c:451 armv7m_arch_state(): target halted due to debug request, current mode: Thread
xPSR: 0x01000000 pc: 0x00001128
Debug: 207 8555 target.c:365 target_process_reset(): Waiting for halted stated as appropriate
Debug: 209 11834 command.c:78 script_command(): script_command - resume
Debug: 210 11834 command.c:95 script_command(): script_command - resume, argv[0]=ocd_resume
Debug: 211 11834 armv7m.c:127 armv7m_restore_context():
Debug: 212 11836 target.c:639 target_call_event_callbacks(): target event 1
Debug: 213 11836 cortex_m3.c:610 cortex_m3_resume(): target resumed at 0x1128
Debug: 215 13530 command.c:78 script_command(): script_command - poll
Debug: 216 13530 command.c:95 script_command(): script_command - poll, argv[0]=ocd_poll
User: 217 13531 target.c:875 target_arch_state(): target state: running
$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reset halt
JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
value captured during scan didn't pass the requested check: captured: 0x00 check_value: 0x01 check_mask: 0x0f
in_handler reported a failed check
Invalid ACK in SWJDP transaction
target state: halted
target halted due to debug request, current mode: Thread
xPSR: 0x01000000 pc: 0x00001128
> resume
> poll
target state: running
(but not working - even reset run fails)
using
target cortex_m3 little 0
Script started on Sun Aug 24 20:28:53 2008
$ openocd -d3 -f wiggler2.cfg -f rdk-idm.cfg
Open On-Chip Debugger 1.0 (2008-08-01-20:44) svn:885M
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
Debug: 4 1 configuration.c:88 find_file(): found /home/rincewind/.openocd/wiggler2.cfg
Debug: 6 1 command.c:78 script_command(): script_command - interface
Debug: 7 1 command.c:95 script_command(): script_command - interface, argv[0]=ocd_interface
Debug: 8 1 command.c:95 script_command(): script_command - interface, argv[1]=parport
Debug: 10 1 command.c:78 script_command(): script_command - parport_port
Debug: 11 1 command.c:95 script_command(): script_command - parport_port, argv[0]=ocd_parport_port
Debug: 12 1 command.c:95 script_command(): script_command - parport_port, argv[1]=0
Debug: 14 2 command.c:78 script_command(): script_command - parport_cable
Debug: 15 2 command.c:95 script_command(): script_command - parport_cable, argv[0]=ocd_parport_cable
Debug: 16 2 command.c:95 script_command(): script_command - parport_cable, argv[1]=wiggler2
Debug: 18 3 command.c:78 script_command(): script_command - jtag_speed
Debug: 19 3 command.c:95 script_command(): script_command - jtag_speed, argv[0]=ocd_jtag_speed
Debug: 20 3 command.c:95 script_command(): script_command - jtag_speed, argv[1]=0
Debug: 21 3 jtag.c:1880 handle_jtag_speed_command(): handle jtag speed
User: 22 3 command.c:359 command_print(): jtag_speed: 0
Debug: 23 3 configuration.c:88 find_file(): found /home/rincewind/.openocd/rdk-idm.cfg
Debug: 25 3 command.c:78 script_command(): script_command - jtag_nsrst_delay
Debug: 26 4 command.c:95 script_command(): script_command - jtag_nsrst_delay, argv[0]=ocd_jtag_nsrst_delay
Debug: 27 4 command.c:95 script_command(): script_command - jtag_nsrst_delay, argv[1]=150
Debug: 29 4 command.c:78 script_command(): script_command - jtag_ntrst_delay
Debug: 30 4 command.c:95 script_command(): script_command - jtag_ntrst_delay, argv[0]=ocd_jtag_ntrst_delay
Debug: 31 4 command.c:95 script_command(): script_command - jtag_ntrst_delay, argv[1]=150
Debug: 33 4 command.c:78 script_command(): script_command - reset_config
Debug: 34 4 command.c:95 script_command(): script_command - reset_config, argv[0]=ocd_reset_config
Debug: 35 4 command.c:95 script_command(): script_command - reset_config, argv[1]=trst_and_srst
Debug: 37 4 command.c:78 script_command(): script_command - jtag_device
Debug: 38 4 command.c:95 script_command(): script_command - jtag_device, argv[0]=ocd_jtag_device
Debug: 39 4 command.c:95 script_command(): script_command - jtag_device, argv[1]=4
Debug: 40 4 command.c:95 script_command(): script_command - jtag_device, argv[2]=0x1
Debug: 41 4 command.c:95 script_command(): script_command - jtag_device, argv[3]=0xf
Debug: 42 4 command.c:95 script_command(): script_command - jtag_device, argv[4]=0xe
Debug: 44 4 command.c:78 script_command(): script_command - target
Debug: 45 4 command.c:95 script_command(): script_command - target, argv[0]=ocd_target
Debug: 46 4 command.c:95 script_command(): script_command - target, argv[1]=cortex_m3
Debug: 47 4 command.c:95 script_command(): script_command - target, argv[2]=little
Debug: 48 4 command.c:95 script_command(): script_command - target, argv[3]=0
Debug: 50 4 command.c:78 script_command(): script_command - working_area
Debug: 51 4 command.c:95 script_command(): script_command - working_area, argv[0]=ocd_working_area
Debug: 52 4 command.c:95 script_command(): script_command - working_area, argv[1]=0
Debug: 53 5 command.c:95 script_command(): script_command - working_area, argv[2]=0x20000000
Debug: 54 5 command.c:95 script_command(): script_command - working_area, argv[3]=0x4000
Debug: 55 5 command.c:95 script_command(): script_command - working_area, argv[4]=nobackup
Debug: 57 5 command.c:78 script_command(): script_command - bank
Debug: 58 5 command.c:95 script_command(): script_command - bank, argv[0]=ocd_flash_bank
Debug: 59 5 command.c:95 script_command(): script_command - bank, argv[1]=stellaris
Debug: 60 5 command.c:95 script_command(): script_command - bank, argv[2]=0
Debug: 61 5 command.c:95 script_command(): script_command - bank, argv[3]=0
Debug: 62 5 command.c:95 script_command(): script_command - bank, argv[4]=0
Debug: 63 5 command.c:95 script_command(): script_command - bank, argv[5]=0
Debug: 64 5 command.c:95 script_command(): script_command - bank, argv[6]=0
Debug: 66 5 command.c:78 script_command(): script_command - init
Debug: 67 5 command.c:95 script_command(): script_command - init, argv[0]=ocd_init
Debug: 68 6 openocd.c:91 handle_init_command(): target init complete
Debug: 69 6 parport.c:349 parport_init(): opening /dev/parport0...
Debug: 70 6 parport.c:361 parport_init(): ...open
Debug: 71 47 parport.c:233 parport_reset(): trst: 0, srst: 0
Debug: 72 47 openocd.c:98 handle_init_command(): jtag interface init complete
Debug: 73 47 jtag.c:1558 jtag_init_inner(): Init JTAG chain
Debug: 74 47 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 75 47 jtag.c:1296 jtag_reset_callback(): -
Debug: 76 47 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 77 47 jtag.c:1296 jtag_reset_callback(): -
Info: 78 51 jtag.c:1413 jtag_examine_chain(): JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
Debug: 79 51 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 80 51 jtag.c:1296 jtag_reset_callback(): -
Debug: 81 51 openocd.c:104 handle_init_command(): jtag init complete
Debug: 82 51 cortex_swjdp.c:946 ahbap_debugport_init():
Debug: 83 58 cortex_swjdp.c:990 ahbap_debugport_init(): AHB-AP ID Register 0x14770011, Debug ROM Address 0xe00ff003
Debug: 84 60 target.c:1102 target_read_u32(): address: 0xe000ed00, value: 0x411fc231
Debug: 85 60 cortex_m3.c:1336 cortex_m3_examine(): CORTEX-M3 processor detected
Debug: 86 60 cortex_m3.c:1337 cortex_m3_examine(): cpuid: 0x411fc231
Debug: 87 62 target.c:1102 target_read_u32(): address: 0xe000e004, value: 0x00000001
Debug: 88 63 target.c:1102 target_read_u32(): address: 0xe000e100, value: 0x00020000
Debug: 89 63 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[0] = 0x00020000
Debug: 90 65 target.c:1102 target_read_u32(): address: 0xe000e104, value: 0x00000000
Debug: 91 65 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[1] = 0x00000000
Debug: 92 67 target.c:1102 target_read_u32(): address: 0xe0002000, value: 0x00000261
Debug: 93 67 cortex_m3.c:1360 cortex_m3_examine(): FPB fpcr 0x261, numcode 6, numlit 2
Debug: 94 69 target.c:1102 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 95 69 openocd.c:107 handle_init_command(): jtag examine complete
Debug: 96 69 openocd.c:113 handle_init_command(): flash init complete
Debug: 97 69 openocd.c:117 handle_init_command(): NAND init complete
Debug: 98 69 openocd.c:121 handle_init_command(): pld init complete
Warning: 99 69 telnet_server.c:627 telnet_init(): no telnet port specified, using default port 4444
Warning: 100 69 gdb_server.c:2019 gdb_init(): no gdb port specified, using default port 3333
Debug: 101 70 gdb_server.c:2034 gdb_init(): gdb service for target cortex_m3 at port 3333
Warning: 102 70 tcl_server.c:178 tcl_init(): no tcl port specified, using default port 6666
Info: 103 2621 server.c:81 add_connection(): accepting 'telnet' connection from 0
Debug: 105 4940 command.c:78 script_command(): script_command - reset
Debug: 106 4940 command.c:95 script_command(): script_command - reset, argv[0]=ocd_reset
Debug: 107 4940 command.c:95 script_command(): script_command - reset, argv[1]=halt
Debug: 108 4940 jtag.c:1602 jtag_init_reset(): Trying to bring the JTAG controller to life by asserting TRST / TLR
Debug: 109 4941 jtag.c:998 jtag_add_reset(): SRST line released
Debug: 110 4941 jtag.c:1017 jtag_add_reset(): TRST line asserted
Debug: 111 4941 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 112 4941 jtag.c:1296 jtag_reset_callback(): -
Debug: 113 4941 jtag.c:994 jtag_add_reset(): SRST line asserted
Debug: 114 4941 jtag.c:1017 jtag_add_reset(): TRST line asserted
Debug: 115 4941 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 116 4941 jtag.c:1296 jtag_reset_callback(): -
Debug: 117 4941 jtag.c:994 jtag_add_reset(): SRST line asserted
Debug: 118 4941 jtag.c:998 jtag_add_reset(): SRST line released
Debug: 119 4941 parport.c:233 parport_reset(): trst: 1, srst: 0
Debug: 120 5091 parport.c:233 parport_reset(): trst: 1, srst: 1
Debug: 121 5092 parport.c:233 parport_reset(): trst: 0, srst: 1
Debug: 122 5242 parport.c:233 parport_reset(): trst: 0, srst: 0
Debug: 123 5542 jtag.c:1558 jtag_init_inner(): Init JTAG chain
Debug: 124 5542 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 125 5542 jtag.c:1296 jtag_reset_callback(): -
Info: 126 5546 jtag.c:1413 jtag_examine_chain(): JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
Debug: 127 5546 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug: 128 5546 jtag.c:1296 jtag_reset_callback(): -
Debug: 130 5546 cortex_swjdp.c:946 ahbap_debugport_init():
Debug: 131 5552 cortex_swjdp.c:990 ahbap_debugport_init(): AHB-AP ID Register 0x14770011, Debug ROM Address 0xe00ff003
Debug: 132 5555 target.c:1102 target_read_u32(): address: 0xe000ed00, value: 0x411fc231
Debug: 133 5555 cortex_m3.c:1336 cortex_m3_examine(): CORTEX-M3 processor detected
Debug: 134 5555 cortex_m3.c:1337 cortex_m3_examine(): cpuid: 0x411fc231
Debug: 135 5557 target.c:1102 target_read_u32(): address: 0xe000e004, value: 0x00000001
Debug: 136 5558 target.c:1102 target_read_u32(): address: 0xe000e100, value: 0x00020000
Debug: 137 5558 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[0] = 0x00020000
Debug: 138 5560 target.c:1102 target_read_u32(): address: 0xe000e104, value: 0x00000000
Debug: 139 5560 cortex_m3.c:1345 cortex_m3_examine(): interrupt enable[1] = 0x00000000
Debug: 140 5562 target.c:1102 target_read_u32(): address: 0xe0002000, value: 0x00000260
Debug: 141 5562 cortex_m3.c:1360 cortex_m3_examine(): FPB fpcr 0x260, numcode 6, numlit 2
Debug: 142 5564 target.c:1102 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 143 5564 cortex_m3.c:679 cortex_m3_assert_reset(): target->state: unknown
Debug: 144 5568 jtag.c:994 jtag_add_reset(): SRST line asserted
Debug: 145 5568 parport.c:233 parport_reset(): trst: 0, srst: 1
Debug: 146 5769 cortex_m3.c:452 cortex_m3_halt(): target->state: reset
Debug: 147 5769 cortex_m3.c:775 cortex_m3_deassert_reset(): target->state: reset
Debug: 148 5769 jtag.c:998 jtag_add_reset(): SRST line released
Debug: 149 5769 parport.c:233 parport_reset(): trst: 0, srst: 0
Warning: 150 6069 jtag.c:1212 jtag_check_value(): value captured during scan didn't pass the requested check: captured: 0x00 check_value: 0x01 check_mask: 0x0f
Warning: 151 6069 jtag.c:1172 jtag_read_buffer(): in_handler reported a failed check
Debug: 152 6072 cortex_m3.c:404 cortex_m3_poll(): Exit from reset with dcb_dhcsr 0x0
Debug: 153 6073 cortex_m3.c:179 cortex_m3_endreset_event(): DCB_DEMCR = 0x00001121
Debug: 154 6075 target.c:1170 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 155 6079 target.c:1170 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 156 6080 target.c:1170 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 157 6082 target.c:1170 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 158 6083 target.c:1170 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 159 6085 target.c:1170 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 160 6086 target.c:1170 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 161 6088 target.c:1170 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 162 6090 target.c:1170 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 163 6091 target.c:1170 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 164 6093 target.c:1170 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 165 6094 target.c:1170 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 166 6096 target.c:1170 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 167 6097 target.c:1170 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 168 6099 target.c:1170 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 169 6100 target.c:1170 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 170 6102 target.c:1170 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 171 6104 target.c:1170 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 172 6105 target.c:1170 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 173 6107 target.c:1170 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 174 6108 target.c:1170 target_write_u32(): address: 0xe0001058, value: 0x00000000
User: 176 6114 target.c:1671 target_wait_state(): waiting for target halted...
Error: 178 6770 target.c:1677 target_wait_state(): timed out while waiting for target halted
Warning: 179 6770 target.c:344 target_process_reset(): Failed to reset target into halted mode - issuing halt
Debug: 180 6770 cortex_m3.c:452 cortex_m3_halt(): target->state: running
Debug: 181 6771 target.c:365 target_process_reset(): Waiting for halted stated as appropriate
Debug: 182 6773 cortex_m3.c:303 cortex_m3_debug_entry():
Debug: 183 6777 cortex_m3.c:111 cortex_m3_clear_halt(): NVIC_DFSR 0x1
Debug: 184 6784 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 0 value 0x0
Debug: 185 6789 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 1 value 0xba
Debug: 186 6794 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 2 value 0x0
Debug: 187 6799 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 3 value 0x1
Debug: 188 6804 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 4 value 0x20000000
Debug: 189 6809 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 5 value 0x20001368
Debug: 190 6814 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 6 value 0x0
Debug: 191 6819 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 7 value 0x6
Debug: 192 6824 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 8 value 0x57e5
Debug: 193 6829 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 9 value 0x0
Debug: 194 6833 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 10 value 0x16
Debug: 195 6839 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 11 value 0x13
Debug: 196 6843 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 12 value 0x0
Debug: 197 6848 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 13 value 0x20001340
Debug: 198 6853 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 14 value 0x905
Debug: 199 6858 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 15 value 0x3340
Debug: 200 6863 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 16 value 0x61000000
Debug: 201 6868 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 17 value 0x20001340
Debug: 202 6873 cortex_m3.c:1130 cortex_m3_load_core_reg_u32(): load from core reg 18 value 0x15004240
Debug: 203 6877 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 19 value 0x0
Debug: 204 6883 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 20 value 0x0
Debug: 205 6887 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 21 value 0x0
Debug: 206 6892 cortex_m3.c:1156 cortex_m3_load_core_reg_u32(): load from special reg 22 value 0x0
Debug: 207 6892 cortex_m3.c:363 cortex_m3_debug_entry(): entered debug state in core mode: Thread at PC 0x3340, target->state: halted
Debug: 208 6892 target.c:639 target_call_event_callbacks(): target event 0
User: 209 6892 target.c:875 target_arch_state(): target state: halted
User: 210 6893 armv7m.c:451 armv7m_arch_state(): target halted due to debug request, current mode: Thread
xPSR: 0x61000000 pc: 0x00003340
Debug: 212 14059 command.c:78 script_command(): script_command - resume
Debug: 213 14059 command.c:95 script_command(): script_command - resume, argv[0]=ocd_resume
Debug: 214 14059 armv7m.c:127 armv7m_restore_context():
Debug: 215 14061 target.c:639 target_call_event_callbacks(): target event 1
Debug: 216 14061 cortex_m3.c:610 cortex_m3_resume(): target resumed at 0x3340
$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reset halt
JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
value captured during scan didn't pass the requested check: captured: 0x00 check_value: 0x01 check_mask: 0x0f
in_handler reported a failed check
waiting for target halted...
timed out while waiting for target halted
Failed to reset target into halted mode - issuing halt
target state: halted
target halted due to debug request, current mode: Thread
xPSR: 0x61000000 pc: 0x00003340
> resume
# Board Config for Luminary Micro
# LM3S6918 RDK-IDM-B Intelligent Display Module
#daemon configuration
#telnet_port 4444
#gdb_port 3333
jtag_nsrst_delay 150
jtag_ntrst_delay 150
reset_config trst_and_srst
#reset_config srst_only
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
#target cortex_m3 little 0 lm3s
target cortex_m3 little 0
# 4k working area at base of ram
working_area 0 0x20000000 0x4000 nobackup
#flash configuration
flash bank stellaris 0 0 0 0 0
proc flashit {args} {
flash probe 0
stellaris mass_erase 0
flash write_bank 0 $args 0
}
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