> > > I'm running openocd on EP9307(arm925t) CPU, as a HOST.
> > > and target is EP9307 and ARM926t with EP9307 GPIO.
> >
> > src/jtag/ep93xx.c is obviously broken.
> >
> > original author's way should be this.
>
> Sorry, it was a wrong patch.
> attchment is a good one.
Sorry, again.
forget attachment.
Index: src/jtag/ep93xx.c
===================================================================
--- src/jtag/ep93xx.c (revision 1183)
+++ src/jtag/ep93xx.c (working copy)
@@ -37,6 +37,7 @@
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
+#include <time.h>
#include <sys/mman.h>
#include <unistd.h>
#include <fcntl.h>
@@ -90,20 +91,20 @@
if (tck)
output_value |= TCK_BIT;
else
- output_value &= TCK_BIT;
+ output_value &= ~TCK_BIT;
if (tms)
output_value |= TMS_BIT;
else
- output_value &= TMS_BIT;
+ output_value &= ~TMS_BIT;
if (tdi)
output_value |= TDI_BIT;
else
- output_value &= TDI_BIT;
+ output_value &= ~TDI_BIT;
*gpio_data_register = output_value;
- nanosleep(ep93xx_zzzz);
+ nanosleep(&ep93xx_zzzz, NULL);
}
/* (1) assert or (0) deassert reset lines */
@@ -112,15 +113,15 @@
if (trst == 0)
output_value |= TRST_BIT;
else if (trst == 1)
- output_value &= TRST_BIT;
+ output_value &= ~TRST_BIT;
if (srst == 0)
output_value |= SRST_BIT;
else if (srst == 1)
- output_value &= SRST_BIT;
+ output_value &= ~SRST_BIT;
*gpio_data_register = output_value;
- nanosleep(ep93xx_zzzz);
+ nanosleep(&ep93xx_zzzz, NULL);
}
int ep93xx_speed(int speed)
@@ -218,7 +219,7 @@
*/
output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
*gpio_data_register = output_value;
- nanosleep(ep93xx_zzzz);
+ nanosleep(&ep93xx_zzzz, NULL);
/*
* Configure the direction register. 1 = output, 0 = input.
@@ -226,7 +227,7 @@
*gpio_data_direction_register =
TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
- nanosleep(ep93xx_zzzz);
+ nanosleep(&ep93xx_zzzz, NULL);
return ERROR_OK;
}
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