Oyvind - See Below.
============================
Rahul,
duane> I presume, based on your OPENOCD script the following:
duane> (A) You RESET and let the board run, ie: "reset run"
rahul> Yes, this is the only option that works.
rahul> I am not able to use "reset halt" or "reset init" to halt the
rahul> target immediately after reset.
The limitation is your chip. Read the data sheet for the imx21.
I believe you will find a statement that says something like this:
Perhaps - spread across many chapters of the manual.
1) At reset the SDRAM is not configured.
2) Until the sdram is configured - any access to sdram will cause an
abort.
3) The same is true for any other chip select.
When you use "reset halt" - OpenOCD stops the CPU at the reset vector,
ie: 0x00000000
(or 0xffff0000 depends on the chip)
thus, you cannot access sdram until you use a series of "mww ADDRESS
DATA"
to configure the sdram, and example of this can be found in
${INSTALLDIR}/lib/board
- at91rm9200-dk.cfg
- eir.cfg
- hammer.cfg
What is missing is the one for your board.
=======================
rahul > [log from init, and reset halt]
rahul> Why do we get this "invalid mode value - communication failure"?
Hmm, not sure I wonder if the nrtst and trst signal are tied together on
your board, or perhaps inside the chip.
You could check the schematic, - inside the chip - is harder to know
other then the data sheet.
1) See the openocd manual about 'reset config'
2) Perhaps Oyvind can speak up about this (he might have to go back and
read the earlier posts to catch up)
=======================
rahul> (gdb) set *(0xC0200000)=5
rauhl> [above does not work]
Don't forget the "mon mww 0xc0200000 5"
Hmm, can you try other memory locations.
ie: the UART....
you should be able to write to the data register and see a byte come out
on (hyperterm) or type a key on (hyperterm) and see the RXREADY bit set
to true, and if you display the rx data register, then display the
status bit again - the RX READY should go away.
====
end
====
-Duane.
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