Hi, Sorry for getting back to you after a while. I was finally able to solve all the issues with CSB735 board (OpenOCD rev: 1187 and latest 1264).
(1) I let the target run for some time to let the flash bootloader initialize the PLL's and SDRAM. GDB works fine and I am able to load programs into RAM and debug them. Here is the monolithic config file and .gdbinit that works with rev 1187. I have also attached the imx21.cfg and csb735_imx21.cfg files for latest syntax. Duane was right: The "remoteaddresssize 16" bug that I mentioned earlier was because of the .gdbinit file in my HOME directory that I used for debugging MSP430. I did not know that irrespective of the directory where you invoke gdb from, it always sources the .gdbinit in HOME directory before searching for one in the local directory. I had the right .gdbinit in my local directory, but a different one in my HOME directory. ---- openocd.cfg ---- # OpenOCD daemon configuration telnet_port 4444 gdb_port 3333 gdb_memory_map enable gdb_detach resume #interface interface ft2232 ft2232_device_desc "Olimex OpenOCD JTAG" ft2232_layout olimex-jtag ft2232_vid_pid 0x15ba 0x0003 jtag_khz 1000 reset_config trst_and_srst srst_pulls_trst # jtag scan chain # format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) jtag_device 4 0x1 0x1 0xe jtag_nsrst_delay 200 jtag_ntrst_delay 200 #target configuration target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs arm7_9 dcc_downloads enable #dedicate 32KB working area inside RAM working_area 0 0xC0800000 0x8000 nobackup #Spansion s29gl512n 32MB * 16-bit flash ROM flash bank cfi 0xC8000000 0x4000000 2 2 0 #Initialize the target init #Let the target run for 500 ms so that the bootloader #can initialize the PLL's and SDRAM reset run sleep 500 halt ---- .gdbinit ---- target remote localhost:3333 set endian little ------------------- (2) Earlier, I had been unable to get the target to halt right after reset. This was because the reset_config needs srst_pulls_trst. I realized this by uncommenting a LOG_DEBUG statement in arm7_9_poll() to display the value of the debug status register right after reset. It showed that the value was equal to the tap id (= tap reset after which IDCODE instruction is loaded by default)! Now, reset halt works fine. Note: I haven't added the PLL and SDRAM initialization code to my scripts as I am not using "reset halt" right now. I will do that as and when I need it and will post it for submission. (3) While debugging this problem, I noticed that the variable arm7_9->debug_entry_from_reset was not set to 1 anywhere in the code, but was checked while clearing the halt condition in arm7_9_clear_halt(). I think it should be set whenever the user issues "reset halt" (in assert_reset()) and should be reset in clear_halt(). I have attached the corresponding patch. -Rahul. On Mon, Dec 8, 2008 at 3:23 AM, Alan Carvalho de Assis <[email protected]>wrote: > Hi Duane, > > On Sun, Dec 7, 2008 at 1:43 PM, Duane Ellis <[email protected]> > wrote: > > Alan/Fabio, > > > > The two of you seem to have *vast* knowledge about the IMX series. > > And access to all kinds of IMX boards. > > > > Perhaps one of you two could spend some time and help Rahul noodle this > > problem out? > > Or perhaps figure this out on some other IMX board. > > > > Yes, we can make some tests here. Please note we didn't get success > using OpenOCD with J-Link (IAR firmware) on iMX27. Everything appear > works fine, OpenOCD detects board correctly but when gdb sends any > command we get many errors. > > Using a FTDI based interface everything works fine. > > > -Duane. > > Regards, > > Alan >
imx21.cfg
Description: Binary data
csb735_imx21.cfg
Description: Binary data
Index: src/target/arm7_9_common.c
===================================================================
--- src/target/arm7_9_common.c (revision 1264)
+++ src/target/arm7_9_common.c (working copy)
@@ -838,6 +838,8 @@
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
}
+ /* When the code comes out of reset, it is halted. */
+ arm7_9->debug_entry_from_reset = 1;
}
/* here we should issue a srst only, but we may have to assert trst as well */
@@ -916,6 +918,10 @@
* restore the register in that case
*/
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
+ /* Reset the flag indicating that target went into debug state
+ * right after reset.
+ */
+ arm7_9->debug_entry_from_reset = 0;
}
else
{
@@ -926,6 +932,10 @@
if (arm7_9->debug_entry_from_reset)
{
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
+ /* Reset the flag indicating that target went into debug state
+ * right after reset.
+ */
+ arm7_9->debug_entry_from_reset = 0;
}
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
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