Greetings,
I've been using OpenOCD for a few years now. I've had great success
using it with the STM32 family of processors. I've just moved to a
new platform with the AT91SAM9G20 processor from Atmel.
I'm having a bit of trouble using the new processor in combination
with the Amontec JTAGKey. I'm sourcing the config from
target/at91sam9260.cfg.
If I power off the board and JTAGKey then start OpenOCD it starts
cleanly. It will function fine until I wish to "reset init" to get
the processor to load any configuration I need to do and get the
processor to a known state.
A "reset init" returns this:
------------------ snip -----------------------------------
JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (Manufacturer:
0x01f, Part: 0x7926, Version: 0x0)
JTAG Tap/device matched
BUG: debug re-entry from system speed access shouldn't be handled here
PC was not 0. Does this target need srst_pulls_trst?
target state: halted
target halted in ARM state due to debug-request, current mode: Undefined
cpsr: 0x6000009b pc: 0x00000650
MMU: disabled, D-Cache: disabled, I-Cache: disabled
-------------------snip -------------------------------
Any further "reset" will give:
------------------ snip -------------------
JTAG communication failure, check connection, JTAG interface, target power etc.
trying to validate configured JTAG chain anyway...
Could not validate JTAG scan chain, IR mismatch, scan returned 0x3F.
tap=at91sam9g20.cpu pos=0 expected 0x1 got 3
Could not validate JTAG chain, continuing anyway...
TAP at91sam9g20.cpu:
value captured during scan didn't pass the requested check:
captured: 0x0F check_value: 0x01 check_mask: 0x0F
in_handler: w/o "in_value", mismatch in SIR
TAP at91sam9g20.cpu:
value captured during scan didn't pass the requested check:
captured: 0x0F check_value: 0x01 check_mask: 0x0F
in_handler: w/o "in_value", mismatch in SIR
Runtime error, file "embedded:startup.tcl", line 176:
examine-fails: -104
in procedure 'ocd_process_reset'
called at file "embedded:startup.tcl", line 175
Runtime error, file "command.c", line 456:
------------------snip ------------------
Now if I try to restart OpenOCD I get:
--------------------snip ------------------
Open On-Chip Debugger 1.0 (2009-03-02-12:42) svn:1395
BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
jtag_speed: 5
use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled
Error: JTAG communication failure, check connection, JTAG interface,
target power etc.
Error: trying to validate configured JTAG chain anyway...
Error: Could not validate JTAG scan chain, IR mismatch, scan returned
0x3F. tap=at91sam9g20.cpu pos=0 expected 0x1 got 3
Warn : Could not validate JTAG chain, continuing anyway...
Warn : TAP at91sam9g20.cpu:
Warn : value captured during scan didn't pass the requested check:
Warn : captured: 0x0F check_value: 0x01 check_mask: 0x0F
Warn : in_handler: w/o "in_value", mismatch in SIR
Warn : TAP at91sam9g20.cpu:
Warn : value captured during scan didn't pass the requested check:
Warn : captured: 0x0F check_value: 0x01 check_mask: 0x0F
Warn : in_handler: w/o "in_value", mismatch in SIR
Warn : no tcl port specified, using default port 6666
--------------------snip -----------------
My config looks like this:
------------snip -------------
#daemon configuration
telnet_port 4444
gdb_port 3333
#interface
interface ft2232
ft2232_device_desc "Amontec JTAGkey"
ft2232_vid_pid 0x0403 0xcff8
ft2232_layout jtagkey
set CHIPNAME at91sam9g20
set ENDIAN little
set CPUTAPID 0x0792603f
# chip
source [find target/at91sam9260.cfg]
jtag_speed 5
$_TARGETNAME configure -event reset-init {
# at reset chip runs at 32khz
jtag_khz 8
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main
oscillator
sleep 20 # wait 20 ms
mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
sleep 10 # wait 10 ms
mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA
Register for 198,656MHz
sleep 20 # wait 20 ms
mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
sleep 10 # wait 10 ms
mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA
is selected
sleep 10 # wait 10 ms
# Now run at anything fast... ie: 10mhz!
jtag_khz 10000 # Increase JTAG Speed to 6 MHz
arm7_9 dcc_downloads enable # Enable faster DCC downloads
}
#this chip has more sram
# Internal sram2 memory
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000
-work-area-size 0x1000 -work-area-backup 1
#gdb
gdb_memory_map enable
arm7_9 dbgrq enable
------------------------snip --------------------
Another error on startup that can happen is this:
--------- Startup Error 2--------
Open On-Chip Debugger 1.0 (2009-03-02-12:42) svn:1395
BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS
$URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
jtag_speed: 5
use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled
Info : JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f
(Manufacturer: 0x01f, Part: 0x7926, Version: 0x0)
Info : JTAG Tap/device matched
Warn : no tcl port specified, using default port 6666
Warn : DBGACK set while target was in unknown state. Reset or initialize target.
Error: BUG: debug re-entry from system speed access shouldn't be handled here
Error: unknown debug reason: 6
target state: halted
target halted in ARM state due to undefined, current mode: Undefined
cpsr: 0x6000009b pc: 0x000004cc
MMU: disabled, D-Cache: disabled, I-Cache: enabled
----------------------------------- End Startup Error 2
---------------------------
Any help with this processor will be greatly appreciated. I'm trying
to load and debug my bootloader with this jtag.
Thank you,
Rob Emanuele
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