The follow patch improves algorithm performance slightly by only marking
registers that has really changed as dirty.
Tested with flash writing for STM32.
With the latest changes I can now get the following performance:
STM32-P103 board, FT2232 JTAG adapter
16 kB, jtag_khz 500
download to target 440ms
flash algoritm 430ms
overhead 140ms
Total 1.01s, approx 15kB/s
16 kB, jtag_khz 3000
download to target 120ms
flash algoritm 430ms
overhead 130ms
Total 680ms, approx 23kB/s
This works with a configured 72 MHz clock on the target,
in my case from the preprogrammed board test application.
The performance of the target flash controller is now the main
limiting factor.
Regards
Magnus
Index: .
===================================================================
--- . (revision 1438)
+++ . (working copy)
@@ -449,10 +449,15 @@
for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
{
- LOG_DEBUG("restoring register %s with value 0x%8.8x",
armv7m->core_cache->reg_list[i].name, context[i]);
- buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32,
context[i]);
- armv7m->core_cache->reg_list[i].valid = 1;
- armv7m->core_cache->reg_list[i].dirty = 1;
+ u32 regvalue;
+ regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value,
0, 32);
+ if (regvalue != context[i])
+ {
+ LOG_DEBUG("restoring register %s with value 0x%8.8x",
armv7m->core_cache->reg_list[i].name, context[i]);
+ buf_set_u32(armv7m->core_cache->reg_list[i].value, 0,
32, context[i]);
+ armv7m->core_cache->reg_list[i].valid = 1;
+ armv7m->core_cache->reg_list[i].dirty = 1;
+ }
}
armv7m->core_mode = core_mode;
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