jie.zeng wrote:
> Again with line no.
> 2105 static int cfi_probe(struct flash_bank_s *bank)
> 2106 {
> /* snip */
>
> 2140 cfi_command(bank, 0x55, command);
> 2141 if((retval = target_write_memory(target,
> flash_address(bank, 0, unlock2), bank->bus_ 2141 width, 1, command)) !
> = ERROR_OK)
> 2142 {
> 2143 return retval;
> 2144 }
> /* snip */
>
>
>> The address depends on your layout, depends on the chip and bus width.
>>
> I'm not sure. I thought that address must match the flash interface
> specification. In this case, from the flash's datasheet where descripted
> that. And also some other flash datasheet point the same thing as below:
> Autoselect stage (cycle, addr, data)
> Manfacturer ID(word) (1st, 555, AA) (2nd, 2AA, 55) (3rd, 555, 90)
> Manfacturer ID(byte) (1st, AAA, AA) (2nd, 555, 55) (3rd, AAA, 90)
>
> Notice the address 0x2AA and 0x555, it's not 0x2aa * bus_width, but the
> source code it is. Why?
>
If you have multiple flashs wired up on 1 bus, then the address lines
between CPU and flash are shifted, requiring correction. The addresses
in the datasheet are *flash* addresses, not *CPU* addresses.
In case flash_width == bus_width, they are the same.
cu
Michael
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