On Tue, 2009-06-02 at 08:37 +0200, Michael Schwingen wrote: > >> > > I'm not sure. I thought that address must match the flash interface > > specification. In this case, from the flash's datasheet where descripted > > that. And also some other flash datasheet point the same thing as below: > > Autoselect stage (cycle, addr, data) > > Manfacturer ID(word) (1st, 555, AA) (2nd, 2AA, 55) (3rd, 555, 90) > > Manfacturer ID(byte) (1st, AAA, AA) (2nd, 555, 55) (3rd, AAA, 90) > > > > Notice the address 0x2AA and 0x555, it's not 0x2aa * bus_width, but the > > source code it is. Why? > > > If you have multiple flashs wired up on 1 bus, then the address lines > between CPU and flash are shifted, requiring correction. The addresses > in the datasheet are *flash* addresses, not *CPU* addresses. > In case flash_width == bus_width, they are the same.
Maybe I got your word. Lets go on. If we want to access a register in the board, we must pass the base address which tell cpu where the register reside and a proper offset(depends on bus-width), right? If the offset is not fix the datasheet, how the cpu can access that reg correctly? In my opinion, the base is 0x10000000 in this case. The offset(in fact its on-chip addr) from datasheet(flash) are 0x2aa(word) and 0x555(byte). So CPU write memory should use the address 0x100002AA or 0x10000555. But now cpu use a wrong address which is 0x10000554. The result is that cannot get right ManufacturerID and probe failure. Regards -- ZJ _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
