hello, all sorry, I repeat the message again because nobody answer it. I test the JTAG interface with Logic Analyze Device, today . I found some fact as below.
1. the jtag_khz will affect the TCK of JTAG. When 6000, It will be 6MHz of the TCK, when 3000, the TCK will be 3MHz. But if I change the jtag_khz beyond the 6000, the TCK will fix in 6MHz. Can anybody explain the reason for me? 2. nSRST and nTRST I configure the system reset and t reset as below: reset_config trst_and_srst But the result I got show that signal on the nSRST and nTRST pin are hold in HIGH. They never fall down to generate a reset . Can anybody explain the reason for me? The attach file is my config file. thank you very much. best regards wangqiang 2009/7/28 Qiang Wang <[email protected]>: > hello, > I use the following configuration. Does it mean that , the system > reset and t reset signal will be assert when openocd started. > > # The configuration of the reset signals available on > # the JTAG interface AND the target. > reset_config trst_and_srst > > best regards > wangqiang >
openocd_v2.cfg
Description: Binary data
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