Holger Freyther wrote:
> Hey,
>
> today Matt Hsu and me sat together to look into why OpenOCD does not work on
> the beagle board. We have found and fixed some issues with the code, it
> should
> make it more robust and we have fixed the root cause for us.
>
> cortex_a8_dap_read_coreregister_u32 only returned 0x0 for the registers, this
> was due the instruction written to the ITR register was not executed. We will
> have to enable bit 13 of DSCR to enable the execution of ITR.
>
> The attached patch series fixes the problem for me and matt. The patches were
> done in teamwork..
>
> regards
> z.
>
>
>
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>
This is nice work but I have some points that need careful
consideration and testing:
The usual way for OpenOCD targets to check if a PROCESSOR_HALTED flag
has been set is not to do it in the halt command but rather in the poll
command.
This in general improves performance when using long roundtrip
interfaces like USB.
This does not affect stability but only moves the actual run state
detection, and affect the halt and resume commands.
Some other checks lite testing for DTRRXfull and wait for previous
instruction patch definetly improves stability but they are performance
killer especially for debug work like single stepping.
Perhaps we need a debugmode=FAST / debugmode = STABLE flag to control
speed vs stability.
When developing the cortex_a8 code I had the "enable ITR for code
execution" in the init script. In general we try put put this kind of
target initialisations in TCL setup/reset scripts.
The relevant part of my omap3_dbginit scrip is:
# DAP AP 1 is connected to the L4 EMU, emulation, trace and debug
modules
dap apsel 1
mww 0x54011FB0 0xC5ACCE55 4
# Clear Sticky Power Down status Bit to enable access to the
registers in the Core Power Domain
mdw 0x54011314
# set DBGEN signal
mww 0x5401d030 0x00002000
# enable execute instruction and halting debug mode
mww 0x54011088 0x00006000
# DAP AP 0 is connected to the L3 interconnect and memory bus
dap apsel 0
I hope this can be of use.
Best regards,
Magnus
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