Øyvind, Dave, Øyvind Harboe wrote: > On Tue, Aug 25, 2009 at 4:33 PM, Dirk Behme<[email protected]> wrote: >> Øyvind Harboe wrote: >>> I have committed all but 01_openocd_beagle.patch to hopefully get things >>> moving along.... >>> >>> 01_openocd_beagle.patch is problematic because it modifies the behavior >>> for *all* targets. >>> >>> Thoughts? >> You might have noticed that I'm not really an expert of OpenOCD's code ;) >> >> Is anything like >> >> if(omap3) { >> /* >> * Add a bunch of clocks after TLR entry to force SWD reset (newer >> * ARM cores; just in case, ~50 cycles), switch on ICEpick power >> * domains (for some TI parts, ~100 cycles), etc >> */ >> jtag_set_error(interface_jtag_add_runtest(100, TAP_RESET)); >> } >> >> possible? Or, probably better, enable/configure this by an external >> configuration (TCL?) variable/parameter? > > We need some more general mechanism. OpenOCD shouldn't > litter it's lower layers w/target specific hacks.
Any proposal how to do this that it can be applied? Thanks Dirk _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
