On Monday 31 August 2009, Dirk Behme wrote:
> >> Is anything like
> >>
> >> if(omap3) {
> >> /*
> >> * Add a bunch of clocks after TLR entry to force SWD reset (newer
> >> * ARM cores; just in case, ~50 cycles), switch on ICEpick power
> >> * domains (for some TI parts, ~100 cycles), etc
> >> */
> >> jtag_set_error(interface_jtag_add_runtest(100, TAP_RESET));
> >> }
> >>
> >> possible? Or, probably better, enable/configure this by an external
> >> configuration (TCL?) variable/parameter?
> >
> > We need some more general mechanism. OpenOCD shouldn't
> > litter it's lower layers w/target specific hacks.
>
> Any proposal how to do this that it can be applied?
When I came up with that I was mostly after a quick fix to
get a Beagle talking ... my thoughts on how to generalize
it were to just always issue 100 extra TCK cycles before
exiting the Test-Logic-Reset (TLR) state.
But as Øyvind noted, that quick fix doesn't quite work that
way ... the 100 cycles are not in TLR.
Two steps seem needed:
- come up with code adding <N> TCK cycles in TLR;
- make sure *all* TLR exit paths use that code
The latter is a bit tricky since the state management is a
bit scattered.
- Dave
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