The same sequence works on my arm1136. However, when you put a scope to SRST signal you will find out that it is actually high (ie not asserted). At least this is what I found on my setup (with olimex)
On Tue, 2009-10-13 at 23:07 -0700, David Brownell wrote: > On Tuesday 13 October 2009, michal smulski wrote: > > arm11 has a bug in that you cannot at the same time assert srst to the > > arm11 core and access its JTAG logic. Asserting srst will disable TAP > > logic. > > Maybe *some* processors do, but I just fired up an OMAP2420 > and found that it's not true: > > jtag_reset 1 1 > jtag_reset 0 1 > jtag arp_init > ... all the scan chain checks work, three active TAPs > > That's an arm1136 based core. The active taps were an ICEpick-B, > the ARM1136, an ETB ... so at the JTAG level there seem to be no > issues like that. > > > On Tuesday 13 October 2009, Øyvind Harboe wrote: > > Can someone help me explain what the effects of asserting > > srst on an arm11 is? > > On that chip, it just keeps parts of the system in reset, > while leaving the TAP alone. This isn't a new part at all; > I think this particular board is almost three years old. > > > > Does anyone know how to safely reset an arm11 into the > > halted state? > > Well it *said* that it halted fine after "reset halt". > And it acted OK then too; "flash probe" worked etc. > > So I'd think the current code is behaving, modulo issues > you might have with iMX31 ... > > - Dave _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
