On Friday 16 October 2009, Øyvind Harboe wrote:
> On Wed, Oct 14, 2009 at 7:03 PM, David Brownell <[email protected]> wrote:
> > On Tuesday 13 October 2009, Øyvind Harboe wrote:
> >> > So I'd think the current code is behaving, modulo issues
> >> > you might have with iMX31 ...
> >>
> >> The currrent code target/arm11* code doesn't assert srst,
> >> it just issues a halt during assert.
> >
> > A quick skim of the docs suggests the right way to get a
> > halt after SRST involves setting halt mode, then setting
> > the reset bit in the vector catch hardware.
>
> Patch anyone? :-) I've got iMX31 hardware to test on. I tried
> this quickly, but it didn't work first try...
See the appended ... SRST is working just fine, despite the
comments in the current code. I think iMX31 must have a few
quirks in that space.
The vector catch is a bit dicey, but I've seen that fire too.
The only caveats for now: (a) use the "reset-assert" code
to reset, not SRST, and (b) lower the JTAG clock, since it
really does catch reset very early ... before kicking in the
PLLs that allow faster clocking!!
- Dave
================== CUT HERE
Teach ARM11 how to use:
- the new "reset-assert" event
- vector catch to implement "reset halt"
- use SRST more like other cores do.
Tested on OMAP2420, where vector catch seems to work ok with the
reset-assert case, but not SRST ... not clear what's up with that.
> reset halt
...
Debug entry: VCR vector catch
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000001d3 pc: 0x00000000
>
If using SRST, it just warns that it didn't halt soon enough.
---
src/target/arm11.c | 65 ++++++++++++++++++++++++++++++++-------------------
1 file changed, 41 insertions(+), 24 deletions(-)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -819,27 +819,41 @@ static int arm11_step(struct target *tar
static int arm11_assert_reset(struct target *target)
{
- int retval;
struct arm11_common *arm11 = target_to_arm11(target);
- retval = arm11_check_init(arm11, NULL);
- if (retval != ERROR_OK)
- return retval;
+ /* FIXME when halt is requested, make it work somehow... */
- target->state = TARGET_UNKNOWN;
+ /* optionally catch reset vector */
+ if (target->reset_halt && !(arm11_vcr & 1))
+ arm11_sc7_set_vcr(arm11, arm11_vcr | 1);
- /* we would very much like to reset into the halted, state,
- * but resetting and halting is second best... */
- if (target->reset_halt)
- {
- CHECK_RETVAL(target_halt(target));
+ /* Issue some kind of warm reset. */
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+ /* REVISIT handle "pulls" cases, if there's
+ * hardware that needs them to work.
+ */
+ jtag_add_reset(0, 1);
+ } else {
+ LOG_ERROR("%s: how to reset?", target_name(target));
+ return ERROR_FAIL;
}
+ /* registers are now invalid */
+ register_cache_invalidate(arm11->arm.core_cache);
+
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+}
/* srst is funny. We can not do *anything* else while it's asserted
* and it has unkonwn side effects. Make sure no other code runs
* meanwhile.
*
+ * (That's not true on OMAP2 chips; maybe an iMX3* series bug?)
+ *
* Code below assumes srst:
*
* - Causes power-on-reset (but of what parts of the system?). Bug
@@ -860,26 +874,29 @@ static int arm11_assert_reset(struct tar
* state?
*/
- jtag_add_reset(0, 1);
- jtag_add_reset(0, 0);
+static int arm11_deassert_reset(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+ int retval;
- /* How long do we have to wait? */
- jtag_add_sleep(5000);
+ /* be certain SRST is off */
+ jtag_add_reset(0, 0);
- /* un-mess up TAP state */
- jtag_add_tlr();
+ retval = arm11_poll(target);
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- {
- return retval;
+ if (target->reset_halt) {
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("%s: ran after reset and before halt ...",
+ target_name(target));
+ if ((retval = target_halt(target)) != ERROR_OK)
+ return retval;
+ }
}
- return ERROR_OK;
-}
+ /* restore vector catch config */
+ if (target->reset_halt && !(arm11_vcr & 1))
+ arm11_sc7_set_vcr(arm11, arm11_vcr);
-static int arm11_deassert_reset(struct target *target)
-{
return ERROR_OK;
}
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