On Sun, Dec 20, 2009 at 10:54 PM, Catalin Patulea <[email protected]> wrote: > On Sun, Dec 20, 2009 at 4:19 PM, Øyvind Harboe <[email protected]> > wrote: >> The interface is going to be near useless for a lot of development >> without it. > I am certainly open to suggestions. The ByteBlaster (parallel dongle > with the same JTAG pinout) also does not have a TRST output. Some > Altera FPGA devices simply do not have a TRST pin [1 note (6)], and as > far as I know the JTAG state machine can emulate a TRST from any state > in a bounded number of transitions (7 clocks I think it was).
That's only on a very theoretical level. TRST will e.g. reset the embedded ice whereas TMS (7 clocks) will only reset the JTAG state machine. > The USB-Blaster does have two unused outputs, which are used in > Altera's Active Serial programming mode, but any assignment of TRST > and SRST between them would be arbitrary and not necessarily > correspond to any particular board. > > How about two driver commands which specify the function of the two > outputs, as unused, TRST or SRST? Sounds reasonable to me. > > [1] http://www.altera.com/literature/dp/flex10k/epf10k70.pdf > -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
