On Sunday 20 December 2009, Øyvind Harboe wrote: > That's only on a very theoretical level. TRST will e.g. reset the > embedded ice whereas TMS (7 clocks) will only reset the JTAG > state machine.
Actually, on the chips I've looked at TRST by itself does the same as the five-clock TMS thing. ARM7/ARM9 EmbeddedICE modules will, as I recall, not reset internal state given just such a JTAG reset. Some ARMs do however map an SRST+TRST reset so it performs the same action as a power-up reset. That's all irrelevant for FPGA and CPLD usage though. :) - Dave _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
