And the debug_level 3 log of the reset command: >> reset > JTAG tap: imx31.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: > 0xb900, ver: 0x2) > JTAG tap: imx31.cpu tap/device found: 0x07b3601d (mfg: 0x00e, part: > 0x7b36, ver: 0x0) > TAP imx31.whatchacallit does not have IDCODE > JTAG tap: imx31.smda tap/device found: 0x2190101d (mfg: 0x00e, part: > 0x1901, ver: 0x2) > found ARM1136 > invalid mode value encountered 28 > target state: halted > unrecognized psr mode: 0x1c > target halted in Thumb state due to undefined, current mode: UNRECOGNIZED > cpsr: 0x004056bc pc: 0x004056b8
Debug: 254 1184962 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_reset Debug: 255 1184962 command.c:133 script_debug(): command - reset ocd_reset Debug: 257 1184962 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_target names Debug: 258 1184962 command.c:133 script_debug(): command - ocd_target ocd_target names Debug: 259 1184962 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu invoke-event reset-start Debug: 260 1184962 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu invoke-event reset-start Debug: 261 1184962 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init-reset Debug: 262 1184962 command.c:133 script_debug(): command - ocd_jtag ocd_jtag arp_init-reset Debug: 263 1184962 core.c:1451 jtag_init_reset(): Initializing with hard TRST+SRST reset Debug: 264 1184962 parport.c:179 parport_reset(): trst: 1, srst: 0 Debug: 265 1184962 core.c:692 jtag_add_reset(): TRST line asserted Debug: 266 1184962 parport.c:179 parport_reset(): trst: 1, srst: 1 Debug: 267 1184962 core.c:667 jtag_add_reset(): SRST line asserted Debug: 268 1184962 parport.c:179 parport_reset(): trst: 0, srst: 1 Debug: 269 1184962 core.c:697 jtag_add_reset(): TRST line released Debug: 270 1184962 core.c:321 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 271 1184962 parport.c:179 parport_reset(): trst: 0, srst: 0 Debug: 272 1184962 core.c:672 jtag_add_reset(): SRST line released Debug: 273 1184967 core.c:1364 jtag_init_inner(): Init JTAG chain Debug: 274 1184967 core.c:321 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 275 1184967 core.c:1017 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS Debug: 276 1184967 core.c:321 jtag_call_event_callbacks(): jtag event: TAP reset Info : 277 1184970 core.c:917 jtag_examine_chain_display(): JTAG tap: imx31.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2) Info : 278 1184970 core.c:917 jtag_examine_chain_display(): JTAG tap: imx31.cpu tap/device found: 0x07b3601d (mfg: 0x00e, part: 0x7b36, ver: 0x0) Info : 279 1184970 core.c:1040 jtag_examine_chain(): TAP imx31.whatchacallit does not have IDCODE Info : 280 1184970 core.c:917 jtag_examine_chain_display(): JTAG tap: imx31.smda tap/device found: 0x2190101d (mfg: 0x00e, part: 0x1901, ver: 0x2) Debug: 281 1184970 core.c:1182 jtag_validate_ircapture(): IR capture validation scan Debug: 282 1184970 core.c:1243 jtag_validate_ircapture(): imx31.etb: IR capture 0x01 Debug: 283 1184970 core.c:1243 jtag_validate_ircapture(): imx31.cpu: IR capture 0x01 Debug: 284 1184970 core.c:1243 jtag_validate_ircapture(): imx31.whatchacallit: IR capture 0x00 Debug: 285 1184970 core.c:1243 jtag_validate_ircapture(): imx31.smda: IR capture 0x01 Debug: 286 1184970 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu cget -chain-position Debug: 287 1184970 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu cget -chain-position Debug: 288 1184971 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled imx31.cpu Debug: 289 1184971 command.c:133 script_debug(): command - ocd_jtag ocd_jtag tapisenabled imx31.cpu Debug: 290 1184971 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu arp_examine Debug: 291 1184971 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu arp_examine Info : 292 1184971 arm11.c:1240 arm11_examine(): found ARM1136 Debug: 293 1184971 arm11.c:1258 arm11_examine(): IDCODE 07b3601d IMPLEMENTOR 41 DIDR 15110004 Debug: 294 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu invoke-event reset-assert-pre Debug: 295 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu invoke-event reset-assert-pre Debug: 296 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu cget -chain-position Debug: 297 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu cget -chain-position Debug: 298 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled imx31.cpu Debug: 299 1184972 command.c:133 script_debug(): command - ocd_jtag ocd_jtag tapisenabled imx31.cpu Debug: 300 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu arp_reset assert 0 Debug: 301 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu arp_reset assert 0 Debug: 302 1184972 parport.c:179 parport_reset(): trst: 0, srst: 1 Debug: 303 1184972 core.c:667 jtag_add_reset(): SRST line asserted Debug: 304 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu invoke-event reset-assert-post Debug: 305 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu invoke-event reset-assert-post Debug: 306 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu invoke-event reset-deassert-pre Debug: 307 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu invoke-event reset-deassert-pre Debug: 308 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu cget -chain-position Debug: 309 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu cget -chain-position Debug: 310 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled imx31.cpu Debug: 311 1184972 command.c:133 script_debug(): command - ocd_jtag ocd_jtag tapisenabled imx31.cpu Debug: 312 1184972 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu arp_reset deassert 0 Debug: 313 1184972 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu arp_reset deassert 0 Debug: 314 1184972 parport.c:179 parport_reset(): trst: 0, srst: 0 Debug: 315 1184972 core.c:672 jtag_add_reset(): SRST line released Debug: 316 1184972 core.c:321 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 317 1184972 core.c:537 jtag_add_statemove(): cur_state=RESET goal_state=DRPAUSE Debug: 318 1184979 arm11.c:351 arm11_poll(): enter TARGET_HALTED Debug: 319 1184980 arm_dpm.c:178 dpm_read_reg(): READ: r0, 004056bc Error: 320 1184981 armv4_5.c:189 arm_mode_to_number(): invalid mode value encountered 28 Debug: 321 1184981 armv4_5.c:397 arm_set_cpsr(): set CPSR 0x004056bc: User mode, Thumb state Debug: 322 1184982 arm_dpm.c:178 dpm_read_reg(): READ: r1, 004056bc Debug: 323 1184982 arm_dpm.c:178 dpm_read_reg(): READ: r2, 004056bc Debug: 324 1184983 arm_dpm.c:178 dpm_read_reg(): READ: r3, 004056bc Debug: 325 1184983 arm_dpm.c:178 dpm_read_reg(): READ: r4, 004056bc Debug: 326 1184984 arm_dpm.c:178 dpm_read_reg(): READ: r5, 004056bc Debug: 327 1184984 arm_dpm.c:178 dpm_read_reg(): READ: r6, 004056bc Debug: 328 1184984 arm_dpm.c:178 dpm_read_reg(): READ: r7, 004056bc Debug: 329 1184985 arm_dpm.c:178 dpm_read_reg(): READ: r8, 004056bc Debug: 330 1184985 arm_dpm.c:178 dpm_read_reg(): READ: r9, 004056bc Debug: 331 1184986 arm_dpm.c:178 dpm_read_reg(): READ: r10, 004056bc Debug: 332 1184986 arm_dpm.c:178 dpm_read_reg(): READ: r11, 004056bc Debug: 333 1184987 arm_dpm.c:178 dpm_read_reg(): READ: r12, 004056bc Debug: 334 1184987 arm_dpm.c:178 dpm_read_reg(): READ: sp_usr, 004056bc Debug: 335 1184988 arm_dpm.c:178 dpm_read_reg(): READ: lr_usr, 004056bc Debug: 336 1184988 arm_dpm.c:178 dpm_read_reg(): READ: pc, 004056b8 Debug: 337 1184990 target.c:968 target_call_event_callbacks(): target event 2 (gdb-halt) Debug: 338 1184990 target.c:968 target_call_event_callbacks(): target event 3 (halted) User : 339 1184990 target.c:1234 target_arch_state(): target state: halted Error: 340 1184990 armv4_5.c:152 arm_mode_name(): unrecognized psr mode: 0x1c User : 341 1184990 armv4_5.c:603 arm_arch_state(): target halted in Thumb state due to undefined, current mode: UNRECOGNIZED cpsr: 0x004056bc pc: 0x004056b8 Debug: 342 1184990 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu invoke-event reset-deassert-post Debug: 343 1184990 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu invoke-event reset-deassert-post Debug: 344 1184990 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_imx31.cpu invoke-event reset-end Debug: 345 1184990 command.c:133 script_debug(): command - ocd_imx31.cpu ocd_imx31.cpu invoke-event reset-end Debug: 346 1184990 arm11.c:366 arm11_poll(): enter TARGET_RUNNING After this I am able to halt, though. > halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x200001d3 pc: 0x0040588c and the log: Debug: 347 1214254 command.c:133 script_debug(): command - ocd_command ocd_command type ocd_halt Debug: 348 1214254 command.c:133 script_debug(): command - halt ocd_halt Debug: 350 1214254 target.c:2073 handle_halt_command(): - Debug: 351 1214254 arm11.c:406 arm11_halt(): target->state: running Debug: 352 1214254 core.c:537 jtag_add_statemove(): cur_state=RUN/IDLE goal_state=DRPAUSE Debug: 353 1214255 arm_dpm.c:178 dpm_read_reg(): READ: r0, 43f80000 Debug: 354 1214256 armv4_5.c:397 arm_set_cpsr(): set CPSR 0x200001d3: Supervisor mode, ARM state Debug: 355 1214256 arm_dpm.c:178 dpm_read_reg(): READ: r1, 00012d06 Debug: 356 1214257 arm_dpm.c:178 dpm_read_reg(): READ: r2, 00000004 Debug: 357 1214258 arm_dpm.c:178 dpm_read_reg(): READ: r3, 1fffff4c Debug: 358 1214258 arm_dpm.c:178 dpm_read_reg(): READ: r4, 00000001 Debug: 359 1214259 arm_dpm.c:178 dpm_read_reg(): READ: r5, 000186a0 Debug: 360 1214259 arm_dpm.c:178 dpm_read_reg(): READ: r6, 00000000 Debug: 361 1214259 arm_dpm.c:178 dpm_read_reg(): READ: r7, 1fffc834 Debug: 362 1214260 arm_dpm.c:178 dpm_read_reg(): READ: r8, 00000000 Debug: 363 1214260 arm_dpm.c:178 dpm_read_reg(): READ: r9, 00000001 Debug: 364 1214261 arm_dpm.c:178 dpm_read_reg(): READ: r10, 00000002 Debug: 365 1214261 arm_dpm.c:178 dpm_read_reg(): READ: r11, 000000f0 Debug: 366 1214262 arm_dpm.c:178 dpm_read_reg(): READ: r12, 000000a1 Debug: 367 1214262 arm_dpm.c:178 dpm_read_reg(): READ: sp_svc, 1fffff3c Debug: 368 1214263 arm_dpm.c:178 dpm_read_reg(): READ: lr_svc, 000000a1 Debug: 369 1214264 arm_dpm.c:178 dpm_read_reg(): READ: pc, 0040588c Debug: 370 1214264 target.c:968 target_call_event_callbacks(): target event 2 (gdb-halt) Debug: 371 1214264 target.c:968 target_call_event_callbacks(): target event 3 (halted) User : 372 1214264 target.c:1234 target_arch_state(): target state: halted User : 373 1214264 armv4_5.c:603 arm_arch_state(): target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x200001d3 pc: 0x0040588c And even the registers look a bit better: > reg ===== ARM registers (0) r0 (/32): 0x43F80000 (dirty) (1) r1 (/32): 0x00012D06 (2) r2 (/32): 0x00000004 (3) r3 (/32): 0x1FFFFF4C (4) r4 (/32): 0x00000001 (5) r5 (/32): 0x000186A0 (6) r6 (/32): 0x00000000 (7) r7 (/32): 0x1FFFC834 (8) r8 (/32): 0x00000000 (9) r9 (/32): 0x00000001 (10) r10 (/32): 0x00000002 (11) r11 (/32): 0x000000F0 (12) r12 (/32): 0x000000A1 (13) sp_usr (/32) (14) lr_usr (/32) (15) pc (/32): 0x0040588C but (gdb) load still fails. -- Edgar Grimberg System Developer Zylin AS ZY1000 JTAG Debugger http://www.zylin.com/zy1000.html Phone: (+47) 51 63 25 00 _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
