Hi!
* Freddie Chopin <[email protected]> wrote:
> > Info : 155 2398 core.c:1350 jtag_interface_init(): clock speed 6000 kHz
>
> Are you sure about the 6MHz JTAG clock?
It worked with the SAME configfiles with openocd from 20091229.
> Is the core frequency above 40MHz after reset?
it is set in a procedure in the configfiles.
> Why don't you use standard cfg files?
They are the standard cfg files, but with some additional procedures:
$_TARGETNAME configure -event reset-init { mt_reset_init }
proc mt_erase_lock {} {
flash protect 0 0 7 off
at91sam7 gpnvm 2 set
}
proc mt_reset_init {} {
soft_reset_halt
# RSTC_CR : Reset peripherals
mww 0xfffffd00 0xa5000004
# disable watchdog
mww 0xfffffd44 0x00008000
# enable user reset
mww 0xfffffd08 0xa5000001
# CKGR_MOR : enable the main oscillator
mww 0xfffffc20 0x00000601
sleep 10
# CKGR_PLLR: 96.1097 MHz
mww 0xfffffc2c 0x00481c0e
sleep 10
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
mww 0xfffffc30 0x00000007
sleep 10
# MC_FMR: flash mode (FWS=1,FMCN=60)
mww 0xffffff60 0x003c0100
sleep 100
}
proc mt_flash_bin {IMGFILE} {
mt_reset_init
arm7_9 dcc_downloads enable
sleep 10
flash probe 0
sleep 10
flash write_image erase $IMGFILE 0x00100000 bin
reset run
sleep 10
}
proc mt_flash_hex {HEXFILE} {
mt_reset_init
arm7_9 dcc_downloads enable
sleep 10
flash probe 0
sleep 10
flash write_image erase $HEXFILE 0x00100000 ihex
reset run
sleep 10
}
proc mt_flash_elf {ELFFILE} {
mt_reset_init
arm7_9 dcc_downloads enable
sleep 10
flash probe 0
sleep 10
flash write_image erase $ELFFILE 0x00100000 elf
reset run
sleep 10
}
Timo
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