* David Brownell <[email protected]> wrote:
> I'm suspecting your config files are set up wrong.
That is possible, but they worked with a snapshot from 20091229 (after
commit cba1813d5c017e2d20969bb419a856fe15c5ceef).
> On Sunday 14 February 2010, Timo Boettcher wrote:
> > Info : 155 2398 core.c:1350 jtag_interface_init(): clock speed 6000 kHz
>
> That's fishy. Atmel chips are pretty consistent about always
> running at "slow clock" -- 32 KiHz -- after reset.
>
> Which means the ARM core can't talk to a JTAG clock running
> at 6 MHz.
>
> Suggest you start with "jtag_khz 8" and only jack that speed
> up to something faster once the PLLs are set up and the chip
> is clocked at something faster. (A "reset-init" event handler
> is often the place to do that.)
I put a global "jtag_khz 8" in my config file, no change.
My config file (original without jtag_khz 8) is pasted below,
can you tell me what I am doing wrong there?
I am calling it with
openocd -f openocd/openocd.cfg
-f /usr/share/openocd/scripts/interface/arm-usb-ocd.cfg
-f openocd/openocd-sam7s256.cfg
-c halt -c targets -c poll
-c "mt_flash_bin glow_flash.bin" -c shutdown
Thanks,
Timo
================== begin paste openocd.cfg ===================
gdb_port 3333
telnet_port 4444
=================== end paste openocd.cfg ====================
============== begin paste openocd-sam7s256.cfg ==============
reset_config srst_only srst_pulls_trst
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME sam7se256
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x3f0f0f0f
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000
-work-area-backup 0
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width>
<target_number> [<target_name> <banks> <sectors_per_bank>
<pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { mt_reset_init }
init
proc mt_erase_lock {} {
flash protect 0 0 7 off
at91sam7 gpnvm 2 set
}
proc mt_reset_init {} {
soft_reset_halt
# RSTC_CR : Reset peripherals
mww 0xfffffd00 0xa5000004
# disable watchdog
mww 0xfffffd44 0x00008000
# enable user reset
mww 0xfffffd08 0xa5000001
# CKGR_MOR : enable the main oscillator
mww 0xfffffc20 0x00000601
sleep 10
# CKGR_PLLR: 96.1097 MHz
mww 0xfffffc2c 0x00481c0e
sleep 10
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
mww 0xfffffc30 0x00000007
sleep 10
# MC_FMR: flash mode (FWS=1,FMCN=60)
mww 0xffffff60 0x003c0100
sleep 100
}
proc mt_flash_bin {IMGFILE} {
mt_reset_init
arm7_9 dcc_downloads enable
sleep 10
flash probe 0
sleep 10
flash write_image erase $IMGFILE 0x00100000 bin
reset run
sleep 10
}
proc mt_flash_hex {HEXFILE} {
mt_reset_init
arm7_9 dcc_downloads enable
sleep 10
flash probe 0
sleep 10
flash write_image erase $HEXFILE 0x00100000 ihex
reset run
sleep 10
}
proc mt_flash_elf {ELFFILE} {
mt_reset_init
arm7_9 dcc_downloads enable
sleep 10
flash probe 0
sleep 10
flash write_image erase $ELFFILE 0x00100000 elf
reset run
sleep 10
}
=============== end paste openocd-sam7s256.cfg ===============
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