On Thu, Sep 9, 2010 at 1:07 PM, Øyvind Harboe <[email protected]> wrote:
> On Thu, Sep 9, 2010 at 12:05 PM, Drasko DRASKOVIC
> <[email protected]> wrote:
>> On Thu, Sep 9, 2010 at 11:40 AM, Øyvind Harboe <[email protected]> 
>> wrote:
>>>> Do you have some other ideas based on these new facts ?
>>>
>>> Best suggestion I have is to roll up your sleeves, break out
>>> the low level reference on your ARM core and start reading....
>>
>> Yeap, seems like there is no easy way out. Might be that ARM920T and
>> ARM946 have different cache management, so I have to figure out
>> differences.
>> Btw. I tried : set $pc = $pc + 4, and then continuing, and it ends
>> well, so it really seems like cache issue in the end.
>
> Darn! I was hoping you'd be forced to improve OpenOCD ;-)

I did not say I would not, just that this should confirm cache issue.

So, I got deeper into the subject today. Looking here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.arm9/index.html
and here :
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.arm9/index.html

I can see that AMR946E (the one that I have, not supported by
OpenOCD), and ARM966E (the one supported by OPenOCD, but this one has
not caches) have the same scan chain 15 addressing mode bit order.
This gives me starting point, so I am using existing arm966e target :
target create $_TARGETNAME arm966e -endian big -chain-position my.cpu
-variant arm946e

For the quick and dirty solution, I created int
arm946e_write_memory(struct target *target, uint32_t address, uint32_t
size, uint32_t count, uint8_t *buffer) to replace currently used
arm7_9_write_memory().
Inside it I just call existing arm7_9_write_memory() and then
invalidate the instruction cache, like this :

printf ("Invalidate I$\n");
retval = arm966e_write_cp15(target, 0x0f, 0);

I do not look if caches are I$ is turned on (I know it is), I just
want to invalidate it on every mem write. This should solve the
problem with breakpoint not deleted from the cache. But it does not!
So breakpoint is hit over and over again, like before.

What am I doing wrong ? Does this cache invalidation seem OK ?

BR,
Drasko
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