On Fri, Sep 10, 2010 at 11:42 AM, Øyvind Harboe <[email protected]> wrote: > Not all ARM's can flush cache via CP15. You may have to first > write to the cache, then to physical memory, finally invalidate > via CP15. > > Check out one of the other arm9 variants. It's what it had do to.
This seems to be true only for D$. Looking at code in arm926.c and arm920t.c I$ handling seems prety stright-forward, and similar to what I did. And for this issue (of re-hitting the sam bkpt) I think tha I$ is important, not D$. Even more, I$ can be guilty for re-hitting breakpoint that was deleted, but in the next pass. Not byb not-preventing us single-step after. That is the real problem - single step is prevented, not the brakpoint that lives still in the memory (say that we intentionally wanted to left it there so it can be hit during the next pass. It should still allow us single-stepping further, right ?). So, this sounds more like some other serious problem in interrupt handling. Where to look for a code for this ? BR, Drasko _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
