Mathias K. wrote:
Hello,
Am 24.02.2011 22:27, schrieb Michael Schwingen:
Am 02/24/2011 09:36 AM, schrieb Mathias K.:
this patch add the risc (default) and harvard architecture to the target
structure. Currently
this patch only affect the memory read/write functions.
I am not sure if "RISC" vs. "Harvard" are the right terms.
IIRC, "Harvard" only means separate address busses / spaces for data and
instruction, but does not tell anything about the behaviour on unaligned
or non-machineword accesses.
I think you can't simple abstract this with 8/16/24/32bit access, because in my
case the data bus
has always a 24bit width and the address bus increment is always one (one
address and 3 bytes of
data). There is no alternative alignment how you can describe a byte of this
24bit with a bus
address, thats the problem.
So the problem is that a word (of 24 bits) is supported as the *only*
access type?
In that case, I think we should talk about unaligned accesses insteadof
harvard/risc.
Now the question is how to handle this at the higher layers:
- only allow word-sized accesses - ie. fail all byte-read/write attempts
- invent virtual byte addresses (as word address * 3) and do
read-modify-write cycles in case a single byte shall be written
cu
Michael
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