Hello,
Am 25.02.2011 14:38, schrieb Michael Schwingen: > Mathias K. wrote: >> I think you can't simple abstract this with 8/16/24/32bit access, because in >> my case the data bus >> has always a 24bit width and the address bus increment is always one (one >> address and 3 bytes of >> data). There is no alternative alignment how you can describe a byte of this >> 24bit with a bus >> address, thats the problem. >> > So the problem is that a word (of 24 bits) is supported as the *only* access > type? Yes, thats true. > > In that case, I think we should talk about unaligned accesses insteadof > harvard/risc. Okay, sounds good. > > Now the question is how to handle this at the higher layers: > - only allow word-sized accesses - ie. fail all byte-read/write attempts This should work. GDB as example always read/write the memory or registers with a 32bit access, the highest byte is never used but transfered. > - invent virtual byte addresses (as word address * 3) and do > read-modify-write cycles in case a > single byte shall be written This make the implementation very complicated and no difference to the outside. I think thats not the right way. Regards, Mathias _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
