Hi Øyvind, I hope that patches are correct now. They come on the top pf your changes.
I removed jtag_add_clocks(5) because they are obscure and I think they do not seem to be present at all - I have seen the same beahviour when removing them. If the patches are OK, maybe someone with M4K can test them before commit ? BR, Drasko On Fri, Apr 1, 2011 at 2:53 PM, Øyvind Harboe <[email protected]> wrote: >>> A bit further down: >>> >>> if (t != NULL) >>> free(t); >> >> OK, I see. That's good for write. But for mips_m4k_read_memory() we >> have to byte-swap directly buffer, right ? > > Yes, and for read it's OK as you're supposed to modify the buffer passed in. > >> Hm... I thought I saw in the patches that you removed some >> keep_alive() from the OpenOCD code... Maybe that give us a little >> speed up ? I do not, know that was just an impression, maybe it is not >> true - I did not do the benchmarking. > > keep_alive() could also explain it, yes. > > > > -- > Øyvind Harboe > > Can Zylin Consulting help on your project? > > US toll free 1-866-980-3434 / International +47 51 87 40 27 > > http://www.zylin.com/zy1000.html > ARM7 ARM9 ARM11 XScale Cortex > JTAG debugger and flash programmer >
From 44f121f57523d69997d4748335574e1955fbd370 Mon Sep 17 00:00:00 2001 From: Drasko DRASKOVIC <[email protected]> Date: Fri, 1 Apr 2011 16:24:55 +0200 Subject: [PATCH] Added correct endianess treatment for big endian targets. Now it is possible to use mips_m4k_write_memory() and mips_m4k_read_memory() to correctly set-up SDRAM, as well as bulk data write, which already handled endianess well. Also added correct endianess manipulation in case of fallback from erroneus bulk write to simple write (to avoid byte swapping two times). --- src/target/mips_m4k.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 66 insertions(+), 4 deletions(-) diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 7530cbd..a3fa162 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -864,6 +864,28 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, if (ERROR_OK != retval) return retval; + /* TAP data register is loaded LSB first (little endian) */ + if (target->endianness == TARGET_BIG_ENDIAN) + { + uint32_t i, t32; + uint16_t t16; + + for(i = 0; i < (count*size); i += size) + { + switch(size) + { + case 4: + t32 = le_to_h_u32(&buffer[i]); + h_u32_to_be(&buffer[i], t32); + break; + case 2: + t16 = le_to_h_u16(&buffer[i]); + h_u16_to_be(&buffer[i], t16); + break; + } + } + } + return ERROR_OK; } @@ -889,11 +911,50 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; + uint8_t * t = NULL; + + /* TAP data register is loaded LSB first (little endian) */ + if (target->endianness == TARGET_BIG_ENDIAN) + { + t = malloc(count * sizeof(uint32_t)); + if (t == NULL) + { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + uint32_t i, t32, t16; + for(i = 0; i < (count*size); i += size) + { + switch(size) + { + case 4: + t32 = be_to_h_u32((uint8_t *) &buffer[i]); + h_u32_to_le(&t[i], t32); + break; + case 2: + t16 = be_to_h_u16((uint8_t *) &buffer[i]); + h_u16_to_le(&t[i], t16); + break; + } + } + + buffer = t; + } + /* if noDMA off, use DMAACC mode for memory write */ + int retval; if (ejtag_info->impcode & EJTAG_IMP_NODMA) - return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); + retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); else - return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); + retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); + if (ERROR_OK != retval) + return retval; + + if (t != NULL) + free(t); + + return ERROR_OK; } static int mips_m4k_init_target(struct command_context *cmd_ctx, @@ -1001,6 +1062,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, } uint8_t * t = NULL; + const uint8_t *ec_buffer = buffer; /* endian-corrected buffer */ /* TAP data register is loaded LSB first (little endian) */ if (target->endianness == TARGET_BIG_ENDIAN) @@ -1019,11 +1081,11 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, h_u32_to_le(&t[i], t32); } - buffer = t; + ec_buffer = t; } retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address, - count, (uint32_t*) (void *)buffer); + count, (uint32_t*) (void *)ec_buffer); if (t != NULL) free(t); -- 1.5.6.5
From 56f1cc816fa37b3dd48d6fbf361f8203cb2f3802 Mon Sep 17 00:00:00 2001 From: Drasko DRASKOVIC <[email protected]> Date: Fri, 1 Apr 2011 16:26:39 +0200 Subject: [PATCH] Corrected waiting on PrAcc in wait_for_pracc_rw(). Added necessary check that PrAcc is "1" before FASTDATA access. Added TAP instruction re-sending before every FASTDATA access (seems to be necessary for 14Kc). --- src/target/mips32_pracc.c | 29 +++++++++++++++++++++++++---- 1 files changed, 25 insertions(+), 4 deletions(-) diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index 816f352..8e6d6dc 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -74,6 +74,8 @@ Nico Coesel #include "config.h" #endif +#include <helper/time_support.h> + #include "mips32.h" #include "mips32_pracc.h" @@ -111,16 +113,24 @@ static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { uint32_t ejtag_ctrl; + long long then = timeval_ms(); + int timeout; while (1) { + /* wait for the PrAcc to become "1" */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; - LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); - return ERROR_JTAG_DEVICE_ERROR; + + if ( (timeout = timeval_ms()-then) > 1000 ) + { + LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); + return ERROR_JTAG_DEVICE_ERROR; + } } *ctrl = ejtag_ctrl; @@ -175,7 +185,6 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); - jtag_add_clocks(5); return jtag_execute_queue(); } @@ -193,7 +202,6 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); - jtag_add_clocks(5); int retval; retval = jtag_execute_queue(); if (retval != ERROR_OK) @@ -1023,11 +1031,19 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are if (address != MIPS32_PRACC_FASTDATA_AREA) return ERROR_FAIL; + /* wait PrAcc pending bit for FASTDATA write */ + if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + return retval; + /* Send the load start address */ val = addr; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); mips_ejtag_fastdata_scan(ejtag_info, 1, &val); + /* wait PrAcc pending bit for FASTDATA write */ + if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + return retval; + /* Send the load end address */ val = addr + (count - 1) * 4; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); @@ -1035,7 +1051,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are for (i = 0; i < count; i++) { + /* wait PrAcc pending bit for FASTDATA write */ + if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + return retval; + /* Send the data out using fastdata (clears the access pending bit) */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK) return retval; } -- 1.5.6.5
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