Hi Eric, thanks for the patch!
Some comments. How to handle caches is sufficiently different that I don't think we should try to make a generic model on how to handle them. Check out some of the arm9's that do not have data flushing implemented and how that's handled: write to memory to populate cache, write cache line to physical memory to sync cache and memory, invalidate data cache, then finally invalidate instruction cache. Also, don't you need to flush the data cache somehow before invalidating the data cache? For now ARM targets have implemented the handling of caches and breakpoints in target->type->write_memory() by making single word writes(16 and 32) safe for setting and restoring software breakpoints. If you don't need to, then I think it merits a comment to explain why. -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 87 40 27 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
