On Fri, Jan 6, 2012 at 8:09 AM, Franck JULLIEN <[email protected]> wrote:
> Hi,
>
> Could anyone provide my an output log from the or1200 during the
> simulation with `define OR1200_VERBOSE set ?
I have never used this define, so am not sure what it does when this
is enabled.
Usually all information about the CPU which is logged comes from the
or1200 monitor. You can see ORPSoC (possibly minsoc, too) uses this to
create execution traces. The monitor probes different parts of the RTL
design to indicate what the state of the CPU is after each executed
instruction.
>
> I did a bench with the or1200 cpu only and stimulate the clock and
> reset. I was expecting to see something happen on the
> instruction bus but everything is quiet.
Check all inputs are tied to a value, so there's no undefined (X)
values getting into the system.
You should see the request for the reset PC go out on the instruction bus.
>
> I looked at or1200_genpc.v.
>
> During the simu, pcreg_default get the OR1200_BOOT_ADR after the reset
> and then the log output gives me # l.mtspr writing into PC: xxxxxxxx.
Again, double check that the instruction bus' data and ack signals
(and error/retry, all of them) are tied to a value, otherwise X will
get into the system and it does all sorts of funny stuff.
>
> Is there any documentation on the HDL implementation ?
Nothing official, unfortunately.
Cheers,
Julius
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