Hi, Could anyone provide my an output log from the or1200 during the simulation with `define OR1200_VERBOSE set ?
I did a bench with the or1200 cpu only and stimulate the clock and reset. I was expecting to see something happen on the instruction bus but everything is quiet. I looked at or1200_genpc.v. During the simu, pcreg_default get the OR1200_BOOT_ADR after the reset and then the log output gives me # l.mtspr writing into PC: xxxxxxxx. Is there any documentation on the HDL implementation ? BR, Franck. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
