Hi all: I have recently realised that Wishbone reset signals are handled asynchronously in most OpenRISC-related cores. However, the Wishbone B4 specification states the following about the reset signal:
---------8<---------8<---------8<--------- RULE 3.00 All WISHBONE interfaces MUST initialize themselves at the rising [CLK_I] edge following the assertion of [RST_I]. They MUST stay in the initialized state until the rising [CLK_I] edge that follows the negation of [RST_I]. RULE 3.05 [RST_I] MUST be asserted for at least one complete clock cycle on all WISHBONE interfaces. RULE 3.20 The following MASTER signals MUST be negated at the rising [CLK_I] edge following the assertion of [RST_I], and MUST stay in the negated state until the rising [CLK_I] edge that follows the negation of [RST_I]: [STB_O], [CYC_O]. [...] OBSERVATION 3.15 If a gated clock generator is used, and if the clock is stopped, then the WISHBONE interface is not capable of responding to its [RST_I] signal. ---------8<---------8<---------8<--------- This is from a VHDL example included in the same specification: process( CLK_I ) begin if( rising_edge( CLK_I ) ) then if( RST_I = '1' ) then Q <= B"00000000"; elsif( (STB_I and WE_I) = '1' ) then Q <= DAT_I( 7 downto 0 ); else Q <= Q; end if; end if; end process REG; Note how the reset signal is handled synchronously. However, most Wishbone reset signals are handled asynchronously, like this: always @ (posedge tck_i or posedge rst_i) begin if(rst_i) rd_module_state <= `STATE_rd_idle; else rd_module_state <= rd_module_next_state; end ... For example, I found this in the OpenRISC core. In or1200_defines.v: `define OR1200_RST_EVENT negedge and then in or1200_wb_biu.v: always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin if (wb_rst_i == `OR1200_RST_VALUE) ... Why is the reset signal handled that way? Is it in order to optimise the generated RTL? Does it really matter? In the case of FPGAs, I've been reading this document: Xilinx WP272 Get Smart About Reset: Think Local, Not Global http://www.xilinx.com/support/documentation/white_papers/wp272.pdf From that document: The good news is that 99.99% of the time, the timing of the reset release really doesn't matter. With statistics like that, it isn't surprising that most circuits work. However, if you have ever had one of the circuits that doesn’t work the first time, then maybe you have encountered one of the 0.01% cases and have been unlucky enough to have released the reset at the wrong time. I'm just worried that there might be some timing issues between the Wishbone clock and the Wishbone reset signals if flip-flops can react to changes to both of them at (nearly) the same time. Thanks, R. Diez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
